ARM Interrupt Controller (GICv2)

Supported

ARM v8 (A53) Implementation.

Little Endian Only

ARM v8 EL0 Support

AArch64 and AArch32

ARM v8 EL1 Support

AArch64 and AArch32

ARM v8 EL2 Support

AArch64

ARM v8 EL3 Support

AArch64

ARM v8 Crypto Instruction

Supported

Vector Floating Point (VFP)

As maintained by mainline. No formal acceptance criteria to feature

SIMD support

As maintained by mainline. No formal acceptance criteria to feature.

ARM v7 Support

A9, R5, R4 supported.

ARM v8 Support

A78

Dual Core ARM-R5f

Incomplete coverage of system register set, little endian only

Dual core R5 CPU run-time configuration

Static dual core, no parallel/lock transitioning

Fault Handling

Faults can be externally injected

Tightly coupled Memories

Only globally accessible TCM memory region is accessible.
Flat memory only, no control register implementation

Interrupt Controller

Supported

SLCRs

Very limited functionality. Only dummy registers, except SD is_MMC control.

Multi-core ARM-R52

lockstep support

IPI

Limited Connectivity specific to PMU functionality

Global Registers

Supported

PMU MicroBlaze

Supported

PMU Interrupt Controller

Supported

I/O Peripherals

Not all peripherals are implemented.
Some standard peripherals are slight variations on the actual cores configuration-wise.

Cadence Gigabit Ethernet Controller

1588 not supported.

SD Host Controller Interface (v3.0)

Supported

SD Card model

No SDXC

QSPI controller (excludes Linear and Generic)

Supported

QSPI linear region

No XIP.  Slow emulation performance.

QSPI NOR flash devices

Incomplete but reasonable selection of parts including many modern QSPI capable devices.

OSPI

Supported

UFS

Supported

UART Controller

Supported

SPI controller

Master mode only.

I2C controller

Master mode only.

DDR

Simple flat RAM model, no ECC.

CAN

Supported

CAN-FD

Supported

XADC

Not supported

GPIO

Limited functionality, connects to remote port.

MDIO and Ethernet PHY

Dummy models, show link up on requested PHY using MDIO

USB

Supported - Host mode only.

SATA

Supported

PCI

Supported

DP Model

AUX Communication.
DPCP: DisplayPort Configuration Information.
EDID.

DPDMA

Supported

2 Layers

Supported

Alpha Blending

Supported

Audio

With some unexpected behavior

Dynamic resolution changes

Supported

Multiple pixel formats

Not all

Mali GPU

Not supported

AMBA/AXI bus interconnect system

Simple bus model, no AXI/AMBA-specific features (such as MIDs).
Master IDs and Trustzone (secure versus non-secure) transactions supported.

Bus quality of service monitoring and control

N/A

On Chip Memory

Supported

AXI Performance Monitor (APM)
AXI Trace Monitor (ATM)

N/A

XMPU

Does not return Slave error; CPU does not recognize asynchronous aborts on failed accesses.

XPPU

Does not return Slave error; CPU does not recognize asynchronous aborts on failed accesses.

SMMU

Only supports 64-bit page tables.

Clock/reset controllers for low-power and high power domains

Limited feature set specific to CPU functionality.

Interprocessor Interrupt controller

Supported

PL-based AMS block

N/A

Ability to boot multiple software in different CPUs.

Supported

Create QEMU Machine models from Linux device tree binaries (DTB)s.

Limited to QEMU maintained DTBs only. IPI/HSI generated DTBs unsupported.

FPDDMA

No FCI and no rate-control.

LPDDMA

No FCI and no rate-control.

MTTCG

Supported

Triple Timer Counter (TTC)

Supported

SWDT, WDT

Not Supported

Si570/71

I2C device.  Dummy emulation of clock generator.

RTC

Supported

AES-GCM

Supported; all key sources

SHA3-384

Supported

SHA2-256

Supported

PMC DMAs

Supported

RSA

Supported

ECDSA

Supported

eFUSE

Supported; all documented fields

BBRAM

Supported