|Zynq UltraScale+ MPSoC CG ||Zynq UltraScale+ MPSoC EG||Zynq UltraScale+ MPSoC EV|
This page provides a list of resources to help you get started using the Xilinx Zynq UltraScale+ MPSoC, including pre-built images for Xilinx development boards, tutorials, and example designs. More detailed information can be found by following the links provided on this page.
Whether you're an expert or novice user, the easiest way to get started with a Xilinx development board is to start with a pre-built Linux image for your board. If you're new the Xilinx embedded design flow, the Embedded Design Tutorial is the recommended way to learn the tools and design flow. To build a custom Linux image, it's recommended that you start with a Petalinux BSP for one of the Xilinx boards, and then customize the configuration to suit your needs.
Table of Contents
The pre-built images referenced here are for the Xilinx development boards. These can be loaded on to SD Cards on the Xilinx development boards and you can boot Linux. The Pre-Built Releases Images page includes images for Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC and Zynq-7000.
Evaluation Boards and BSP
PetaLinux Board Support Packages (BSP) and Reference Examples include pre-built boot loaders, system images and bitstreams. Built-in tools allow a single command to deploy and boot these elements to either physical hardware, or to the included full QEMU system emulator. With PetaLinux, developers can have their Xilinx-based hardware booted and running within about 5 minutes after installation; ready for application, library and driver development.
Xilinx provides three development boards for the Zynq UltraScale+ MPSoC devices. For more information, the links below take you back to board-specific pages at Xilinx.com
Each board also comes with a PetaLinux BSP that includes an image, documentation to recreate that image and a design that can be used as a starting point for the hardware user. There is one BSP for each board above. They are called PetaLinux BSPs since the Xilinx PetaLInux tool is used to create these images. The links to them take you back to the PetaLinux Download page at Xilinx.com. Please note that you will need a Xilinx.com login to download these files.
There are other vendors that like Avnet or Digilent. Here are the links to their sites
Xilinx provides a variety of example designs on their development boards for the users. These range from OS, power management and graphics examples. An example design is a snapshot of in time, what this means is that the design is done on a specific Xilinx tool release and not necessarily updated to other tool releases or the current release. The user can take these and update them on their own.
Targeted Reference Designs (TRD)
Xilinx also provides a smaller set of Targeted Reference Designs or TRDs. There are not as many TRDs as Example Designs. However, these TRDs are updated on each major tool release for a set amount of time. The TRDs are fully supported by Xilinx.
Embedded Design Tutorial (EDT)
The Embedded Design Tutorial provides an introduction to using the Xilinx® Vivado® Design Suite flow for using the Zynq UltraScale+ MPSoC device. The examples are targeted for the Xilinx
ZCU102 Rev 1.0 and Rev 1.1 evaluation boards. The latest versions of the EDT use the Vitis™ Unified Software Platform.
Overview of the Embedded Software Stack on a Zynq UltraScale+ MPSoC
The following is an overview of the embedded software stack for a Zynq UltraScale+ MPSoC.
In a Zynq UltraScale+ MPSoC device there is a BootROM for initial bring up of the device. The Configuration and Security Unit (CSU) processor uses the code in the BootROM . In this configuration stage, the BootROM (part of the CSU ROM code) interprets the boot header to configure the system and load the processing system’s (PS) first-stage boot loader (FSBL) code into the on-chip RAM (OCM) in both secure and non-secure boot modes. The boot header defines many boot parameters, including the security mode and which processor should execute the FSBL. The boot header parameters can be found int the Zynq UltraScale+ Device TRM UG1085. During boot, the CSU also loads the PMU user firmware (PMU FW) into the PMU RAM to provide platform management services in conjunction with the PMU ROM. The PMU FW must be present in most systems for the Xilinx-based FSBL and system software. The loading of the FBSL before the PMU Firmware is the default configuration. Some systems will switch the order and have the PMU Firmware loaded first, so there might be other diagrams showing the FSBL and the PMU Firmware swtiched.
The First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with the hardware bitstream (if it exists) and loads the Operating System (OS) Image, Standalone (SA) Image, 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to memory (DDR/TCM/OCM), then takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a code image, bitstream, or generic data. Each of these partitions, if required, can be authenticated and/or decrypted.
The FSBL is loaded into On-Chip Memory (OCM) and handed off by the Configuration and Security Unit (CSU) BootROM after authentication and/or decryption (as required) FSBL.
For more information, go to the Zynq UltraScale+ FSBL page.
Platform Management Unit (PMU) Firmware
The Platform Management Unit (PMU) in Zynq MPSoC has a Microblaze with 32 KB of ROM and 128 KB of RAM. The ROM is pre-loaded with PMU Boot ROM (PBR) which performs pre-boot tasks and enters a service mode. For more details on PMU, PBR and PMUFW load sequence, refer to Platform Management Unit (Chapter-6) in Zynq MPSoC TRM (UG1085). PMU RAM can be loaded with a firmware (PMU Firmware) at run-time and can be used to extend or customize the functionality of PMU. Some part of the RAM is reserved for PBR, leaving around 125.7 KB for PMU Firmware.
For more information, refer to the PMU Firmware and Build PMU firmware pages.
ARM Trusted Firmware
ARM Trusted Firmware (ATF) provides a reference to secure software for ARMv8-A architecture and it provides implementations of various interface standards like PSCI(Power State Coordination Interface) and Secure monitor code for interfacing to Normal world software. Xilinx ARM trusted firmware is based on arm trusted firmware at https://github.com/ARM-software/arm-trusted-firmware.
Xilinx ARM Trusted Firmware tree will be released and available at https://github.com/Xilinx/arm-trusted-firmware.
For more information, go to the ATF page.
U-Boot, short for Universal Boot Loader, is an open source, primary boot loader used in embedded devices to boot the device's operating system kernel that is frequently used in the Linux community. Xilinx uses U-Boot as a second stage boot loader in the Zynq Ultrascale+ devices. For more information about U-Boot visit their page at https://www.denx.de/wiki/U-Boot.
For more information about U-Boot on Zynq Ultrascale+ devices, go to the U-Boot page on this wiki.
On the Zynq UltraScale+ devices, a hypervisor can be used to run more than one virtual machine. There are several hypervisors supported on the Zynq UltraScale+ devices. The list can be found on the Embedded Software EcoSystem Xilinx.com.
For more information regarding hypervisor uses on Zynq UltraScale+, please see the Multi-OS Support (AMP & Hypervisor) page.
Since Linux is the primary OS that people start with on the Zynq UltraScale+ devices, there is more information on it at the Linux page. This includes the two different build tools used to create customer distributions. Xilinx's PetaLinux and Yocto, an open source project that is part of the Linux Foundation. The Linux page also describes how to build your own Linux from the source, and links to information about the Linux drivers that Xilinx provides.
For Zynq UltraScale+ MPSoC Power Management there is a are several wiki pages dedicated to this but a good starting point is the Zynq UltraScale＋ MPSoC Power Management page.
Zynq UltraScale+ provides hardware accelerators to implement integrity, confidentiality, and authentication in system. The Configuration Security Unit (CSU) is the Zynq UltraScale+ functional block that provides interfaces required to implement the secure system. There is also a section in the Zynq UltraScale+ MPSoC Embedded Design Tutorial - (UG1209) about security and secure boot.
For more information, refer to the Zynq Ultrascale+ MPSoC Security Features page.
The following link a list of all the documentation for Zynq UltraScale+ MPSoC from Xilinx.com. This information is hosted on the web but also available with an installation of the Xilinx tool DocNav
The Xilinx Community Forums are places to get answers to questions or search for solutions to problems using Xilinx devices.
The Xilinx Community Portal showcases Xilinx in the Open Source Space and highlights projects using Xilinx products.
The Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to the Zynq UltraScale+ MPSoC. Whether you are starting a new design with Zynq UltraScale+ MPSoC or troubleshooting a problem, use the Zynq UltraScale+ MPSoC solution center to guide you to the right information.
The Multimedia User Guide describes the architecture and features of multimedia systems with PS + PL + VCU IP. Learning about this architecture can help you understand the complete multimedia system, and facilitates integration with third party IP to develop custom multimedia pipelines.
The Xilinx tools provide all required tool chains to compile and link applications for Xilinx supported platforms, create and configure hardware designs, and create bitstreams.
Installing the Xilinx Tools