1. Release Notes

1.1 Steps to Generate ISP Example Design and Build Software Components

Generate ISP Example Design: Begin by generating the ISP Vivado example design, according to the steps outlined in the PG432 ISP Product Guide.

Generate Yocto-based Linux Artifacts: Follow the instructions provided in the Linux section to Yocto Build and Image Generation Guide. In case MIPI is connected to the FPD domain in the Programmable Logic (PL) design, refer to the MIPI stability Answer Record AR000038130 for guidance on addressing the MIPI stability issue.
To address the CDO clock issues in example designs (Non-MCM LIMO/LILO with TILE0), apply the patch from this Answer Record AR000038118.

ISP Firmware Preparation: You can either use the pre-built ISP firmware binary from the generated root filesystem (rootfs) or generate the ISP firmware by following the steps detailed on the ISP Firmware [2025.1] page. If MIPI is connected to the Low Power Domain (LPD) in the PL design, refer to the Answer Record AR000038130 for solutions to the MIPI stability issue.

Load and Validate Artifacts: Once VEK385 board setup is complete (Xylon FMC Card and Sensor Setup), based on the boot mode, copy the artifacts to their respective location. See the Steps to Run ISP Pipeline MIMO/LIMO/LILO section in the Linux build page to load the artifacts onto the target.

1.2 ISP IP/Driver Features

The following table describes the list of ISP features, input/output formats, maximum resolutions, and output paths supported as part of the 2025.1 release.

1.3 Features Not Supported in ISP Stack

• RGB-IR sensor (5 MP)

• Multiple ISP instance combinations for MCM mode:

  • 4 streams on ISP0 + 1 stream on ISP1 instance

  • 3 streams on ISP0 + 2 streams on ISP1 instance

  • 2 streams on ISP0 + 2 streams on ISP1 instance

• Multiple instances of ISP firmware running in AMP mode

1.4 Known Issues

• MCM is validated using a maximum of four sensors operating at 15 fps. Running a pipeline at 30 fps can in the long run lead to frame-drops or pipeline hangs.

• Closing a single pipeline in the MCM use case causes hangs on other running pipelines of the same ISP instance

• If a design includes AXI-Switch and AXI-Broadcaster IPs as part of ISP pipeline, errors are observed while converting pl.dtsi to dtbo because of end point linking issues. To overcome this issue, users have to edit the remote end point in pl.dtsi.

• Memory In Memory Out (MIMO) pipeline with fakesink is not working.

• Live In Live Out (LILO) driver is not validated with designs that have MIPI connected to the FPD in the PL design.

• Closing the media_server application using Ctrl+C causes a core dump. Instead use the pkill -9 isp_media_serve command to close the media_server application.

• Unloading of the ISP overlay using dfx-manager leads to Kernal Crashes. A reboot is needed for rerun.

• Use only the shared Tuning files, custom Tuning Parameters cannot be supported.

1.5 Limitations

• Only a single instance of firmware can be loaded and run on RPU cluster-3, core-0 (R52_6).

• In Non-MCM mode, only two ISP tiles can be validated with four sensors.

• In MCM-mode, the firmware can handle up to 4 MCM streams only on a single ISP.

• 3 ISP Tiles can support max 15 sensors. Due to a XylonFMC + VEK385 board pin limitation, only 4 streams are supported.

• On a VEK385 board, Xylon FMC supports only 3 MIPI interfaces, only MIPI-2 and MIPI-6 is validated. MIPI-5 is not validated due to design limitations.

• An End to End pipeline with 8MP (3840x2160) sensor can achieve up to 15 fps.

• In certain Vivado example designs, ISP SLCR Clocks are not being programmed. See the ISP SLCR Clocks Answer Record AR000038118 for guidance on addressing ISP SLCR Clocks.

• MIPI instability issues are observed with some VEK385 boards. Refer to AR000038130 for guidance on addressing the MIPI stability issue.