DP1.4 RXSS standalone driver

1. Introduction

The DisplayPort 1.4 RX Subsystem (DP RXSS) standalone driver provides a bare‑metal API and a menu‑driven example application to bring up and validate the DP 1.4 receiver pipeline on AMD platforms. The driver targets DisplayPort Sink (RX) use cases and exposes control and status of the DP RX subsystem and associated PHY over a UART console.

• Subsystem: DisplayPort 1.4 RX Subsystem (RXSS)

• Product Guide: DisplayPort 1.4 RX Subsystem Product Guide (PG300)

  • https://docs.amd.com/r/en-US/pg300-v-dp-rxss1?tocId=iA~vJpFpAe84h89yPmT1fg

• The IP‑level architecture, feature set, and configuration options are described in PG300. This page focuses on the standalone driver view: how it is organized, what interfaces and capabilities it exposes, and how to use the RX‑only example.

2. Driver Features

• Support for DisplayPort Sink (RX) capabilities

• Supports multi-stream transport (MST) and single stream transport (SST)

• Dynamic lane support (1, 2, or 4 lanes)

• Dynamic link rate support (1.62/2.7/5.4/8.1 Gb/s)

• Dynamic support for 6, 8, 10, 12, or 16 bits per component (BPC)

• Dynamic support for RGB/YCbCr444/YCbCr422/YCbCr420 color formats

• Supports 16-bit Video PHY (GT) interface

• Supports 2 to 8 channel audio with 44/48 kHz sample rates

• Supports HDCP 1.3 and HDCP 2.2/2.3 decryption in SST

• AXI IIC controller for external peripheral programming

• Supports native or AXI4-Stream video output interface

• Supports single audio stream in MST mode

• Supports SDP packet for static HDR mode

• Supports eDP v1.4b

• Supports DSC and/or forward error correction (FEC) in association with AMD partner

• Supports DSC with HDCP 1.x and HDCP 2.x decryption in SST

• Supports YUV420 colorimetry

• Supports adaptive sync in SST mode

• Supports in-band 3D stereo

For system‑level Linux/Bare‑metal enablement and known gaps across DP 1.4 / DP 2.1 TX/RX, see:
https://amd.atlassian.net/wiki/spaces/XPS/pages/1332678746

3. Implementation

The DP RXSS standalone driver is delivered as part of the standard embeddedsw tree.

• Driver name: xdprxss

• Typical repository path:
  XilinxProcessorIPLib/drivers/dp_rxss/

3.1 Driver layering

The driver stack is organized as:

• Core IP drivers

  • DP RX core driver

  • Video PHY Controller (VPHY) driver
    These handle low‑level register programming, link training, and PHY configuration.

• Subsystem driver (xdprxss)

  • Wraps the DisplayPort 1.4 RX Subsystem instance

  • Provides initialization, configuration, and integration with the supporting IPs via AXI4‑Lite

  • Exposes APIs for control and status of link, lane, and PHY parameters

• Example application (RX‑only)

  • Performs platform initialization (VFMC IO expanders, clocks, resets)

  • Configures DP RXSS in the desired mode (SST configuration for the provided example)

  • Provides a UART menu for:

    • AUX reset

    • Link status reporting

    • VPHY configuration and error status

    • Core information

    • DTG reset (where applicable)

    • Audio/Video MSA attribute and timestamp reporting

On startup, the example prints platform initialization status and confirms that the RX subsystem is enabled in SST mode.

4. Known issues and limitations

For the RX‑only standalone driver example described on this page:

• There are no specific known issues for the basic RX bring‑up flow with SST configuration.

• The example is intended as a bring‑up and debug utility and does not exercise all IP‑level capabilities such as:

  • MST routing and multiple streams

  • Advanced HDCP repeater scenarios

  • DSC/FEC integration flows

Advanced DisplayPort use cases may require additional software (e.g., Linux drivers, framework integration) and system components. For a consolidated view of enabled features and remaining gaps across DP 1.4 and DP 2.1 TX/RX IP and software stacks, refer to:
https://amd.atlassian.net/wiki/spaces/XPS/pages/1332678746

5. Example applications

5.1 DP RX‑only example

The DisplayPort RX Only Example is a standalone bare‑metal application that:

• Initializes the board and platform interfaces used by DP RXSS (VFMC IO expanders, IIC, clocks, resets).

• Initializes and configures the DisplayPort 1.4 RX Subsystem and associated Video PHY.

• Provides a UART‑based text menu to control and inspect:

  • AUX logic (reset)

  • DP link status

  • VPHY configuration and status

  • VPHY error information

  • Core information (DP RXSS)

  • DTG resets (where implemented)

  • Audio/Video MSA attributes and related information

This example is intended to validate basic link bring‑up and RX subsystem integration and to give users a reference for controlling DP RXSS from software.

The UART menu offered by the example is:

6. Example application usage

The usage flow below assumes a typical Zynq UltraScale+ MPSoC board with a DP RX FMC. Adjust board/FMC names as needed for your platform.

6.1 Hardware setup

• Board: e.g. ZCU102 (Zynq UltraScale+ MPSoC)

• FMC / daughter card: DP RX FMC

• Connections:

  • Connect a DisplayPort source (GPU/PC) to the RX connector on the FMC.

• IO expanders / VFMC:

  • Ensure VFMC IO expanders are connected and powered, as the example configures them at startup.

6.2 Vivado design

A typical hardware design contains:

• DisplayPort 1.4 RX Subsystem (DP RXSS) configured as per PG300:

  • Required lane count and link rate

  • Desired color depth and color format support

  • AXI4‑Stream or native video output interface

• Video PHY Controller (VPHY) connected to the DP RXSS GT interface with a 16‑bit data width.

• Processor system (e.g. Zynq UltraScale+ MPSoC PS) with:

  • AXI4‑Lite interconnect to the DP RXSS, VPHY, and IO expanders/IIC

  • Interrupts from DP RXSS and VPHY routed to the processor

Export this design as an XSA for software development in Vitis.

6.3 Vitis / standalone application flow

1. Create platform

   • In Vitis, create a standalone platform project from the exported XSA containing DP RXSS.

2. Create application

   • Create a new application project using this platform.

   • Either select the provided DP RXSS RX‑only example template, or add the RX‑only example source into a new standalone application.

3. Build

   • Build the application to generate the ELF.

4. Run on hardware

   • Program the PL with the bitstream.

   • Load and run the RX‑only ELF on the processor.

6.4 Console interaction

1. Open a UART console at the board’s default settings (for example, 115200‑8‑N‑1).

2. Power on or reset the board.

3. Confirm that the application banner, platform initialization messages, and SST‑mode enable message are printed.

4. Use the UART menu described in Section 5.1 to:

   • Check link and VPHY status

   • Reset AUX or DTG as needed

   • Retrieve core information

   • Retrieve Audio/Video MSA attributes and related status

7. Test log

7.1 RX‑only example boot log

This section provides a reference boot log for the RX‑only example.

8. Sequence Diagram:

The attached document provides a detailed description of the application and driver flow for DP passthrough & Rx only mode.

9. Change log

• 2026.1

  • Initial documentation for DP1.4 RXSS standalone driver.

  • Added:

    • Introduction and product references (PG300, video IP index).

    • Driver features (PG‑style feature list).

    • Implementation overview and driver layering.

    • DP RX‑only example description and usage steps.

    • Reference RX‑only UART boot log.

  • Linked to consolidated DP feature/gap tracking page:
    https://amd.atlassian.net/wiki/spaces/XPS/pages/1332678746