SMPTE UHD‑SDI Transmitter Standalone Driver

1. Introduction

The SMPTE UHD‑SDI Transmitter Subsystem (SDI TXSS) standalone driver provides a bare‑metal API and example applications to bring up and validate UHD‑SDI transmit pipelines on AMD platforms. The driver targets SDI transmit and pass‑through use cases and exposes control and status of the SDI TX and associated RX/audio subsystems through a UART console.

• Subsystem: SMPTE UHD‑SDI Transmitter Subsystem (SDI TXSS)

• Product Guide: SMPTE UHD‑SDI Transmitter Subsystem Product Guide (PG289)

  • https://docs.amd.com/r/en-US/pg289-v-smpte-uhdsdi-tx-ss?tocId=Q5CHbIfnetTn0JSL4ozu3Q

The IP‑level architecture, feature set, and configuration options are described in PG289. This page focuses on the standalone driver view and the SDI pass‑through example.

2. Driver Features

• Support for SMPTE UHD‑SDI transmit capabilities across supported SDI standards (HD‑SDI, 3G‑SDI, 6G‑SDI, 12G‑SDI) as configured in the subsystem

• Supports multi‑rate operation with appropriate SDI mode selection (for example, 3G‑SDI level A) as defined in PG289

• Supports SDI video formats including 720p, 1080i, 1080p, and UHD resolutions as defined in PG289 and within device bandwidth limits

• Supports YCbCr 4:2:2 color format at 10 bits per component for standard UHD‑SDI streams, with additional color format support depending on subsystem configuration

• Provides AXI4‑Stream or native video interfaces (as configured) for integration with upstream video processing pipelines

• Supports embedding of audio into the outgoing SDI stream

• Supports audio extraction from an SDI input used as the source for SDI TX in pass‑through designs

• Supports AES3 (SPDIF) audio capture and playback in conjunction with SDI audio extract/embed paths

• Provides status and control for SDI mode, frame format, resolution, frame rate, color format, pixel clock, and ST352 payload via register interface

• Integrates with AMD clocking and transceiver resources as described in PG289 for supported devices

For the complete and authoritative feature list, refer to the SMPTE UHD‑SDI Transmitter Subsystem Product Guide (PG289):
https://docs.amd.com/r/en-US/pg289-v-smpte-uhdsdi-tx-ss?tocId=Q5CHbIfnetTn0JSL4ozu3Q

3. Implementation

The SDI TXSS standalone driver is delivered as part of the standard embeddedsw tree.

• Driver name: typically xsdi_txss / xv_sdi_txss (per embeddedsw naming)

• Typical repository path:
  XilinxProcessorIPLib/drivers/ (SDI TXSS driver folder)

3.1 Driver layering

The driver stack is organized as:

• Core IP drivers

  • SDI TX core driver

  • (In pass‑through designs) SDI RX core driver

  • Audio extract and embed drivers

  • SPDIF (AES3) drivers
    These handle low‑level register access, mode configuration, and interrupt handling for the respective IP blocks.

• Subsystem / example driver layer

  • Wraps the UHD‑SDI Transmitter Subsystem and any associated RX and audio IP used in the example.

  • Provides initialization and configuration flows for SDI TX, and for SDI RX/audio blocks when used for pass‑through.

  • Exposes APIs for stream information, audio group detection, and control of audio routing.

• Example applications

  • SDI Pass‑Through Example (described on this page)

    • Video pass‑through from SDI RX to SDI TX

    • SDI audio pass‑through and AES3 capture/playback modes

    • UART menu to view status, logs, and debug information

On startup, the example initializes the SDI audio embed and extract driver and registers interrupt handlers for SPDIF RX/TX and SDI audio extract/embed before entering the main menu loop.

4. Known issues and limitations

For the SDI pass‑through standalone driver example:

• There are no specific known issues for the SDI video and audio pass‑through flow corresponding to the reference log in Section 7.1.

• The example is intended as a bring‑up and debug utility and focuses on:

  • Single‑link SDI video pass‑through

  • Embedded audio pass‑through and AES3 capture/playback

• More advanced configurations (multi‑link UHD, additional color formats, custom payloads) depend on the specific IP and board configuration and may require additional software or customization beyond this example.

Refer to PG289 for supported device families, SDI standards, and any IP‑level limitations:
https://docs.amd.com/r/en-US/pg289-v-smpte-uhdsdi-tx-ss?tocId=Q5CHbIfnetTn0JSL4ozu3Q

5. Example applications

5.1 SDI pass‑through example

The SDI Pass Through Example is a standalone bare‑metal application that:

• Initializes the platform and peripheral interfaces required by the SDI TXSS and the associated RX/audio IP used in pass‑through.

• Initializes the SDI Audio Embed and Extract driver.

• Registers interrupt handlers for:

  • SPDIF (AES3) RX

  • SPDIF (AES3) TX

  • SDI Audio Extract

  • SDI Audio Embed

After initialization, it presents a UART‑based main menu:

The Info and related options allow software to query SDI RX/TX stream parameters and SDI audio status.

6. Example application usage

The usage flow below assumes a typical Zynq UltraScale+ MPSoC platform with UHD‑SDI TX and RX subsystems instantiated as described in PG289/PG290.

6.1 Hardware setup

• Board: e.g. ZCU106 or another board with UHD‑SDI TX/RX FMC or on‑board SDI connectors (match your design).

• SDI connections:

  • Connect a valid SDI source to the SDI RX input used as the pass‑through source.

  • Connect the SDI TX output to an SDI monitor or analyzer to observe the transmitted stream.

• Audio connections (optional):

  • For AES3/SPDIF capture and playback, connect the appropriate AES3 input and output ports as provided on your board or FMC.

Ensure SDI‑related clocks, reference clocks, and transceivers are configured as described in PG289 and the board documentation.

6.2 Vivado design

A typical hardware design includes:

• SMPTE UHD‑SDI Transmitter Subsystem (SDI TXSS) configured per PG289.

• An associated SDI RX path (e.g. UHD‑SDI RXSS) when implementing pass‑through from SDI RX to SDI TX.

• Audio extract and embed blocks, and SPDIF (AES3) interfaces for audio routing.

• Processor system (e.g. Zynq UltraScale+ MPSoC PS) with:

  • AXI4‑Lite connections to SDI TX, SDI RX, audio, and SPDIF IP

  • Interrupts from SDI and audio IP routed to the processor

Export the design as an XSA for software development.

6.3 Vitis / standalone application flow

1. Create platform

   • In Vitis, create a standalone platform from the exported XSA containing SDI TX, SDI RX, audio, and SPDIF IP.

2. Create application

   • Create a new application project using this platform.

   • Either choose the SDI Pass Through Example template, or import the example sources into a new standalone application.

3. Build

   • Build the application to generate the ELF.

4. Run on hardware

   • Program the PL with the bitstream.

   • Load and run the SDI pass‑through ELF on the processor.

6.4 Console interaction

1. Open a UART console at the board’s default settings (for example, 115200‑8‑N‑1).

2. Power on or reset the board.

3. Confirm the example banner and initialization messages, including:

   • SDI Pass Through Example banner

   • SDI AUDIO EMBED AND EXTRACT DRIVER ready

   • Successful registration of SPDIF and SDI audio interrupt handlers

4. Use the main menu:

   • i – Show SDI RX and TX stream information

   • z – Show SDI RX/TX log information

   • d – Dump register debug information

   • s – Enable SDI audio pass‑through (embedded audio from SDI RX to SDI TX)

   • a – Enable AES3 audio capture and playback (AES3 input to SDI TX, SDI RX audio to AES3 output)

7. Test log

7.1 SDI pass‑through example log

This section provides a reference log for the SDI pass‑through example.

8. Sequence Diagram:

9. Change log

• 2024.1

  • Initial documentation for SDI TXSS standalone driver pass‑through example.

  • Added:

    • Introduction and PG289 reference.

    • Driver features aligned with SMPTE UHD‑SDI TX subsystem capabilities.

    • Implementation overview and driver layering.

    • SDI pass‑through example description and usage steps.

    • Reference SDI pass‑through UART log.