DP1.4 TXSS standalone driver

1. Introduction:

The DisplayPort 1.4 Transmitter Subsystem (DP TXSS) standalone driver is a bare‑metal (non‑OS) driver that provides a high‑level control interface for the AMD/Xilinx DisplayPort 1.4 TX Subsystem IP (PG299).

The driver abstracts common tasks such as:

• DisplayPort link training

• Link configuration (lane count, link rate, bits‑per‑color)

• EDID read and capability negotiation

• Video timing selection (including custom timings)

• Optional HDCP integration (when enabled in the design)

Product guide reference:
DisplayPort 1.4 TX Subsystem Product Guide (PG299):
https://docs.amd.com/r/en-US/pg299-v-dp-txss1

2. Driver Features

Key capabilities of the DP1.4 TXSS standalone driver include:

• Support for DisplayPort Source (TX) transmissions

• Supports multi-stream transport (MST) and single stream transport (SST)

• Dynamic lane support (1, 2, or 4 lanes)

• Dynamic link rate support (1.62/2.7/5.4/8.1 Gb/s)

• Dynamic support for 6, 8, 10, 12, or 16 bits per component (BPC)

• Dynamic support for RGB/YCbCr444/YCbCr422/YCbCr420 color formats

• Supports 16-bit Video PHY (GT) interface

• Supports 2 to 8 channel audio with 44/48 kHz sample rates

• Supports HDCP 1.3 and HDCP 2.2/2.3 encryption in SST

• Supports native or AXI4-Stream video input interface

• Pixel mode support in native video interface mode

• Supports Linear PCM 2-channel audio format

• Supports single audio stream in MST mode

• Supports SDP packet for static HDR mode

• Supports eDP v1.4b

• Supports DSC and/or forward error correction (FEC) in association with AMD partner Rambus Inc.

• Supports YUV420 colorimetry

• Supports adaptive sync

• Supports in-band 3D stereo

3. Implementation

The standalone DP TX Subsystem driver is implemented as part of the AMD/Xilinx embeddedsw stack.

• Driver name: xdptxss

• Typical repository layout:

  • XilinxProcessorIPLib/drivers/dp_txss/

• Layering:

  • Core drivers

    • Low‑level DP core

    • PHY

    • HDCP (where applicable)

  • Subsystem driver (xdptxss)

    • Wraps and coordinates core drivers

    • Exposes high‑level API for:

      • Link training

      • Resolution and BPC change

      • EDID read

      • Custom timing table registration

      • HDCP enable/disable (if compiled in)

• Applications:

  • Example applications provide menu‑driven tests on top of xdptxss to validate:

    • RX→TX pass‑through

    • HDCP pass‑through

    • TX‑only patterns and mode changes

This structure keeps the DP protocol logic in the driver while leaving board‑specific initialization (I/O expanders, clocking, resets) in the platform/application layer.

4. Known issues and limitations

• None identified for the SST‑only flows documented here:

  • RX→TX pass‑through

  • HDCP‑enabled pass‑through

  • TX‑only demo

For broader protocol and feature gaps (e.g. MST, DSC/FEC, special DP2.1 features), refer to:
https://amd.atlassian.net/wiki/spaces/XPS/pages/1332678746

Board‑specific quirks (for example, missing FMC causing “Failed to set the I2C IO Expander”) can be documented here as needed.

5. Example applications

The DP TXSS standalone driver is validated and demonstrated using multiple example applications:

1. DP Pass‑Through Example (RX→TX)

   • Uses both DP RXSS and DP TXSS

   • Receives video over DP RX and forwards it to DP TX

   • Provides a simple “p - Pass-through design” menu entry to start the flow

2. DP HDCP Pass‑Through Example

   • Extends the pass‑through flow with HDCP enablement

   • Loads encrypted HDCP keys from DP FMC EEPROM (password protected)

   • Provides a menu for:

     • HDCP debug info

     • Link, MSA, and error status

     • EDID pass‑through and retraining

3. DP TX‑Only Example

   • Uses DP TXSS only (no RXSS)

   • Reads EDID from the monitor and trains the link

   • Provides an interactive TX‑only menu to:

     • Change resolution

     • Change bits‑per‑color

     • Change lane count and link rate

     • Change pattern

     • Display MSA values

     • Inspect DPCD and AUX registers

     • Enable/disable audio and VSC

     • Power up/down sink

6. Example application usage

6.1 Hardware and platform setup

1. Hardware

   • Board: Zynq UltraScale+ MPSoC evaluation board (e.g., ZCU102)

   • DP FMC or on‑board DP connectors (depending on design)

   • DP 1.4‑capable monitor

   • Optional DP source (for pass‑through use cases)

2. Vivado / IP Configuration

   • Instantiate:

     • DP RX Subsystem (for pass‑through examples)

     • DP TX Subsystem

     • Video PHY (appropriate GT configuration)

   • Configure DP TXSS for:

     • SST mode

     • Required maximum link rate and lane count

   • Export hardware (XSA).

3. Vitis (or Vitis NG) Platform

   • Create a platform project from the XSA

   • Ensure the BSP includes:

     • DP RXSS driver (for pass‑through)

     • DP TXSS driver (xdptxss)

     • Video PHY driver

     • HDCP/KeyMgmt drivers if using HDCP examples

6.2 Building the example applications

1. Create application project

   • Target the previously created platform

   • Choose the relevant DP example:

     • Pass‑through

     • HDCP pass‑through

     • TX‑only

2. Build

   • Build to generate the .elf

   • Check the linker map for inclusion of DP and PHY drivers

6.3 Running and interacting with the examples

1. Program and run

   • Program the FPGA with the bitstream

   • Load and run the example ELF via Vitis or XSCT

2. Console

   • Open a UART terminal

   • Observe the banner and menu

   • Interact using the prompts

7. Test Logs

7.1 Pass‑through log

7.2 HDCP pass‑through log

7.3 TX‑only log

8. Sequence Diagram

The attached document provides a detailed description of the application and driver flow for DP.

9. Change Log

2025.1

• Initial DP1.4 TXSS standalone driver documentation.

• Captured:

  • Pass‑through (RX→TX) log

  • TX‑only demo log

2026.1

• Added HDCP pass‑through log and flow description.

• Added:

  • Implementation section

  • Known issues and limitations (None)

  • Example applications

  • Example application usage

  • Change log