This is an additional resource for the AMD Versal™ AI Edge Series Gen 2 VEK385 Evaluation Kit and does not replace the official documentation of the https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/vek385.html on AMD.com.

Introduction

The VEK385 Evaluation Kit is equipped with the AMD Versal™ AI Edge Series Gen 2 2VE3858 adaptive SOC, which delivers end-to-end acceleration for AI-driven embedded systems. The kit comes with a breadth of connectivity options, development tools, and example designs to accelerate prototyping across a broad range of embedded markets, including those with high-security, high-reliability, long-lifecycle, and safety-critical applications

Getting Started

This section provides the prep-work, board setup and files needed to boot and run a couple of designs on the VEK385 board. You will need to download files and applications to interface to the boards but you will need no installation or knowledge of the AMD tools to run these on the VEK385.

For board setup and configuration, refer to the VEK385 Board User Guide, UG1712

Prep Work

You will need a terminal interface such as Tera Term or PuTTY to interface to the UART. Please download the tool of your choice before getting started.

It is recommended to use a tool such as Balena Etcher to write the WIC image to the SD card. You can then point this tool to the downloaded ZIP file and it will automatically extract and burn the compressed image.

The VEK385 supports a multi-stage boot process where the primary boot device is OSPI (Octal SPI Flash), and the secondary boot device is an SD/UFS. This section details the steps to run through the boot process:

Download the VEK385 Pre-built Yocto EDF boot images:Downloads
Detailed Build & Boot steps are outlined here: Multi-Stage Image Boot Process

Board Setup

Board setup is quick and easy, the following are the instructions and diagrams for setup.

Please note that there is an SD Card slot on the VEK385 board. The SD card is for storing the boot images for the Versal Device itself. The VEK385 does not have an SD card interface for System controller boot. System Controller firmware can be loaded into the eMMC. The VEK385 board comes with a pre-programmed System Controller image. Refer to the Versal System Controller section of System Controller Updates for information on how to use the System controller BEAM tool and steps to upgrade the system controller image if necessary.

Connect the 12V power Supply to the VEK385 board.
Ensure that the System Controller firmware flashed properly on the eMMC.
Set the Versal Boot mode switch as shown in the below figure.
VEK385 SW1 showing OSPI Mode setting
Connect a USB Type-A to USB Type-C cable between your PC and the VEK385 board.
The VEK385 comes with a USB-C connector for JTAG+UARTs
Evaluation boards have multiple UART connections. When the FTDI-USB cable is plugged in, it will create multiple device nodes on the host PC. The VEK385 Rev B has 4 serial / UART interfaces mapped as follows:
1. Device 0 (JTAG)
2. Device 1 (Versal PS-UART1)
3. Device 2 (Versal PS-UART0)
4. Device 3 (System Controller UART)

Running a design

Use the instructions below to run the design that you have downloaded via the Yocto EDF flow for the VEK385 board, once you have prepared the SD card.

Connect to the Versal UART
1. Ensure the USB Type‑C cable is connected between the host PC and the VEK385 board.
2. On the host PC, identify the UART interface corresponding to Versal PS‑UART1 or PS‑UART0.
Configure the terminal
1. Open your preferred serial terminal application (for example, Tera Term or PuTTY).
2. Select the correct COM port / device node for the chosen Versal UART.
3. Set the serial parameters to:
  - Baud rate: 115200
  - Data bits: 8
  - Parity: None
  - Stop bits: 1
  - Flow control: None
Power up the board
1. Verify that the boot mode switches are set for OSPI + SD boot as described in the Board Setup section.
2. Turn ON the VEK385 board power switch.
Observe the boot log
1. With a successful boot, a log similar to the following appears on the Versal UART terminal.
2. Use this as a reference to verify that the boot process is proceeding correctly.
[0.011]**************************************** [0.043]Xilinx Versal Aiepg2 Platform Loader and Manager [0.080]Release 2025.1 Mar 26 2025 - 02:13:26 [0.116]Platform Version: v1.0 PMC: v1.0, PS: v1.0 [0.154]BOOTMODE: 0x8, MULTIBOOT: 0x0 [0.181]**************************************** [0.366]Non Secure Boot [4.618]PLM Initialization Time [4.641]Boot PDI Load: Started ... [2379.013]Boot PDI Load: Done [2383.509]56.855 ms: ROM Time [2386.171]Total PLM Boot Time NOTICE: TF-A running on Silicon v0.0, RTL v8.6, PS v8.6, PMC v8.6 NOTICE: BL31: Executing from 0xbbf00000 NOTICE: BL31: Secure code at 0x1800000 NOTICE: BL31: Non secure code at 0x40000000 NOTICE: BL31: v2.12.0(debug):v1.1-15203-gf418a6916-dirty NOTICE: BL31: Built : 11:18:22, Mar 19 2025 INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x40000000 U-Boot 2025.01-g5a324e1e94ae-dirty (Mar 26 2025 - 10:13:21 +0000) CPU: Versal Gen 2 Model: AMD Versal VEK385 revA DRAM: 2 GiB (effective 8 GiB) Bootmode: OSPI_MODE ... Hit any key to stop autoboot: 0 starting USB... ... Device 0: Vendor: Generic Rev: 1.98 Prod: Ultra HS-COMBO Type: Removable Hard Disk Capacity: 60874.0 MB = 59.4 GB (124669952 x 512) [... Yocto EDF Linux kernel messages omitted ...] amd-edf login:

VEK385 Example Designs

This section details the list of example designs targeting VEK385.

Sl. No	Example Design	Description	Design URL

Sl. No	Example Design	Description	Design URL
1	HDMI Advanced Subsystem Design	Validates HDMI Transmit (Tx) and Receive (Rx) functionality	HDMI Advanced Subsystem Design
2	NoC2 and DDRMC5 Design	This design uses one Performance AXI traffic generator (TG) and one AXI NoC2 instance, with two interleaved 2x16 LPDDR5 memory controller blocks. The TG writes then reads 256-byte transactions with a linear addressing pattern. The NoC interleaves the traffic across the four 16-bit memory channels.	NoC2-DDRMC5-Design
3	Power States Reference design	The Power States TRD showcases the ability of PLM Firmware to manage and control the power states of various Power Domains within the device. This includes transitioning between different power modes (for example, active, idle, suspend) based on system activity and requirements. Efficient power management is essential for optimizing performance and reducing energy consumption in embedded systems.	GitHub - Xilinx/pm_demo

Versal AI Edge Series Gen 2 VEK385 Evaluation Kit

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