1 Introduction
2 HW IP Features
3 Known issues and limitations
4 Kernel Configuration
5 Devicetree
6 Test procedure
7 Mainline Status
8 ChangeLog
- 8.1 2025.2
9 Related Links

Introduction

This page provides information about the AMD I3C driver, which can be found on AMD/Xilinx Git and mainline as amd-i3c-master.c
The I3C controller supports the v1.0 standard and includes dynamic address assignment, data
transfer to legacy I2C destinations, broadcast, and CCC transfers. The controller can operate as
in the secondary configuration mode.

HW IP Features

MIPI I3C Specification v1.1.1 compatible
Two wire serial interface up to 12.5 MHz
Single data rate (SDR) only Primary Controller
SDR only Target
SDR only Secondary Controller (SC)
Support for direct and broadcast common command codes (CCC)
Support for CCC Retry
Legacy inter-integrated circuit (I2C) support as per the MIPI I3C Specification v1.1.1
Dynamic addressing support
In-band interrupt (IBI)
Hot-Join support

Known issues and limitations

IBI and Hot-Join features not supported

Kernel Configuration

The following config options need to be enabled:
CONFIG_AMD_I3C_MASTER

It depends on I3C and HAS_IOMEM

Devicetree

Refer to Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml for complete description.

Example
The following example shows adding an I3C node to the devicetree:

i3c@80000000 {
        compatible = "xlnx,axi-i3c-1.0";
        reg = <0x80000000 0x10000>;
        clocks = <&zynqmp_clk 71>;
        interrupt-parent = <&imux>;
        interrupts = <0 89 4>;
        #address-cells = <3>;
        #size-cells = <0>;
    };

Test procedure

This section details the getting of values from the sensor interfaced to i3c:

# cat in_accel_x_raw
325

Mainline Status

No Mainlined

ChangeLog

2025.2

Summary

i3c: master: Add AMD I3C bus controller driver

Commits

16a2a853f1bd -i3c: master: Add AMD I3C bus controller driver

AMD Linux I3C driver