Spartan™ UltraScale+™ FPGAs SCU35 Evaluation Kit

Spartan™ UltraScale+™ FPGAs SCU35 Evaluation Kit

board.png

This is an additional resource for the SCU35 Evaluation Kit and does not replace the official documentation of the Spartan UltraScale+ page on AMD.com.

Table of Contents

Introduction

The SCU35 Evaluation Kit is designed to accelerate development with AMD’s Spartan™ UltraScale+™ FPGA family, offering a cost-optimized solution for edge and embedded applications. At its core, the kit features the SU35P device and enables a balance of performance, flexibility, and low power consumption.

This evaluation platform includes a rich set of peripherals and interfaces—such as Pmod connectors, Arduino and Raspberry Pi headers, MikroClick interfaces, Ethernet, USB UART, and JTAG—making it ideal for rapid prototyping and system integration.

Getting Started

This section provides the prep-work, board setup and files needed to boot and run a couple of designs on the SCU35 board. You will need to download files and applications to interface to the boards, but will need no installation or knowledge of the AMD tools to run these on the SCU35.

For board setup and configuration, refer to the SCU35 Evaluation Board User Guide (UG1713) (Note you will need to register for the SCU35 Early Access site to access this link)

Prep Work

Install the 2025.2 Version of Vitis from: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis/2025-2.html

This is required to run the ready PDI and ELF files.

You will need a terminal interface such as Tera Term or PuTTY to interface to the UART to boot the SCU35 board. Download your choice before getting started.

Board Setup

The board setup is quick and easy, below are the instructions and diagrams for setup.

Here is a detailed overview of the board components:

image-20251116-171937.png

We are demonstrating here the JTAG boot mod.

  1. Connect the Power Supply to the SCU35 board.

  2. Set the JTAG Boot mode, by removing the Jumper of J35 header as highlighted below:

    image-20251116-170927.png
  3. Connect the USB to Micro USB cable provided with the kit between the host PC and SCU35 board

  4. Three UART ports should be visible in Device Manager

Running a Design via JTAG using XSDB

This section describes how to use the Vitis XSDB (System Debugger) to program the SCU35 board with a simple design and run a Hello World application.

Prerequisites

  • SCU35 board powered and connected via JTAG (see Board Setup above)

  • UART terminal (Tera Term, PuTTY, etc.) connected at 115200 baud, 8N1

  • Vitis tools installed and XSDB available in your PATH

  • Download example design files (Test_Files.zip):

    • PDI file (scu35_examples_design.pdi)

    • ELF file (hello_scu35.elf)

XSDB Command Sequence

Open a terminal and launch XSDB:

xsdb

Enter the following commands in the XSDB prompt:

# 1. Connect to the hardware connect # 2. List available targets targets # 3. Select the main device ta 1 # 4. Program the device with the PDI file dev p scu35_examples_design.pdi # 5. List targets again to see processor cores targets # 6. Select the processor core (e.g., Hart #0, replace '4' if your index differs) ta 4 # 7. Download the Hello World ELF to the processor dow hello_scu35.elf # 8. Run the application con

Expected Output:
You should see the ELF download progress and, once you run con, the Hello World output should appear on your UART terminal:

image-20251116-171350.png

SCU35 Example Applications

The SCU35_Example_Design implements a MicroBlaze-based embedded system on the FPGA platform, integrating multiple AXI peripherals for I/O and communication. The key components include:

  • MicroBlaze Processor (microblaze_riscv_0):
    Serves as the central processing unit, connected to local memory (DLMB, ILMB) and the debug module (MDM).

  • I/O Interfaces:

    • AXI GPIO: Controls LEDs, DIP switches, push buttons, and PMOD connectors.

    • AXI UARTLite: Provides serial communication via UART.

    • AXI IIC: Enables I2C communication with devices such as EEPROM and sensors (including INA and ACL).

This design is primarily intended to validate FPGA I/O functionality and peripheral integration. It enables testing of:

  • GPIO control for LEDs

  • UART communication for data exchange

  • I2C transactions with external devices (for example, INA700 sensors)

SCU35_Vitis_Apps leverage this MicroBlaze-based system and AXI peripherals to provide flexible I/O and sensor interfacing apart from a simple hello world application. The included Vitis applications demonstrate:

  • GPIO LED Control: Toggling and testing onboard LEDs using AXI GPIO.

  • INA700 Sensor Readout: Retrieving real-time power and temperature data via I2C from onboard INA700 sensors.

Additional Resources

SCU TRD User Guide - https://docs.amd.com/r/en-US/xd332-scu35-trd-ug

Product Page - Spartan UltraScale+

 

© 2025 Advanced Micro Devices, Inc. Privacy Policy