Video Processing Subsystem Standalone Driver

This page gives an overview of the bare-metal driver support for the VPSS standalone driver.

1 Introduction
2 Driver Sources
3 Driver implementation
4 Features
- 4.1 Controller and driver features Supported:
5 Known issues and limitations
6 Example applications
7 Links to examples
8 Example application usage
- 8.1 xv_proc_ss_example:
  - 8.1.1 Example Design Architecture
  - 8.1.2 Expected Output
9 Change Log
- 9.1 2025.1

Introduction

The AMD LogiCORE™ IP Video Processing Subsystem is a collection of video processing IP subcores, bundled together in hardware and software, abstracting the video processing provides the end-user with an out of the box ready to use video processing core, without having to learn about the underlying complexities.

The Video Processing Subsystem enables streamlined integration of various processing blocks including (but not limited to) scaling, deinterlacing, color space conversion and correction, chroma resampling, and frame rate conversion.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver name	path in vitis	Parth in Github

Driver name	path in vitis	Parth in Github
vprocss	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/vprocss	embeddedsw/XilinxProcessorIPLib/drivers/vprocss at master · Xilinx/embeddedsw

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2025.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/vprocss at xlnx_rel_v2025.1 · Xilinx/embeddedsw

The driver source code is organized into different folders. The table below shows the vprocss driver source organization.

Directory	Description

Directory	Description
src	Driver source files, make and cmakelists file
examples	Example applications that show how to use the driver features and video lock for a particular frame rate
doc	Provides the API and data structure details
data	Driver .tcl, .yaml and .mdd file

Note: the AMD embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml file (in the data folder) and CMakeLists.txt (in the src folder) are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver implementation

For a full list of features supported by this IP, see Video Processing Subsystem - PG278

Features

Controller and driver features Supported:

One, two, four, and eight pixel-wide AXI4-Stream video interface
- If deinterlacer is enabled in the data pipeline, then the overall processing subsystem gives one sample per clock equivalent performance
Video resolution support up to 8k at 60 fps. If deinterlacer is enabled in the data pipeline, the maximum video resolution that can be supported is 1080p at 60 fps.
Runtime color space support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
8, 10, 12, and 16 bits per component support
Deinterlacing: supports 32-bit and 64-bit memory address
Scaling
Color space conversion and correction
Chroma resampling between YUV 4:4:4, YUV 4:2:2, YUV 4:2:0
Frame rate conversion using dropped/repeated frames

Known issues and limitations

None

Example applications

Refer to the driver examples directory for VPSS example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to examples

Examples Path:

embeddedsw/XilinxProcessorIPLib/drivers/vprocss/examples at xlnx_rel_v2025.1 · Xilinx/embeddedsw

Test/Application Name	Example source	Description

Test/Application Name	Example source	Description
xv_proc_ss_example	vprocss/examples/src/xv_proc_ss_example.c	This example application is built to demonstrate the functionality of the FrameBuffer Write IP and its video lock for selected resolution on KC705/ZCU102/ZCU104/ZCU106/VCK190 platforms.

Example application usage

xv_proc_ss_example:

The TPG generates video data and sends to Video Processing Subsystem IP for a specified resolution and configuration. Then the video data is transferred through all of the subcores of the VPSS which are enabled based on configuration used in the applications. This processed video data has been sent to Axi4_stream_video_out IP along with a timing control generated through the VTC. If the axi4s_stream_video_out IP receives video data properly within timing generated by the VTC for a selected resolution, then video lock happens properly and the testcase passes. If it does not receive video properly within the timing generated by the VTC, then either video_overflow or video_underflow happens, and the test case results in failure.

Example Design Architecture

A system illustration is shown as below.


                     -----------
                     | Video   |
                     | Timing  |----
                     | Control |    |
                     -----------    |
   ----------        ----------     |   ------------     ----------
   |        |        |        |     --->|   AXI4S  |     | Frame  |
   |  TPG   |  ----> |  VPSS  | ------->| to Video |---->| Buffer |
   |        |        |        |         |    OUT   |     | Write  |
   ----------        ----------         ------------     ----------

Expected Output

VPSS Exdes Test Passed

Change Log

2025.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.1 · embeddedsw/embeddedsw