Video Mixer Standalone Driver

This page gives an overview of the bare-metal driver support for the Video Mixer standalone driver.

1 Introduction
2 Driver Sources
3 Driver implementation
4 Features
- 4.1 Controller and driver features Supported:
5 Known issues and limitations
6 Example applications
7 Links to examples
8 Example application usage
- 8.1 xv_mix_example:
  - 8.1.1 Example Design Architecture
  - 8.1.2 Expected Output
9 Change Log
- 9.1 2025.2
- 9.2 2025.1

Introduction

The AMD LogiCORE™ IP Video Mixer core provides a flexible video processing block for alpha blending and compositing multiple video and/or graphics layers. Support for up to seventeen layers is provided (one main layer and sixteen overlay layers with an optional logo layer), using a combination of video inputs from either memory or streaming video cores (through AXI4-Stream interfaces). The core is programmable through a comprehensive register interface to control frame size, background color, layer position, and the AXI4-Lite interface. A comprehensive set of interrupt status bits is provided for processor monitoring.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver name	path in vitis	Parth in Github

Driver name	path in vitis	Parth in Github
v_mix	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/v_mix	embeddedsw/XilinxProcessorIPLib/drivers/v_mix at master · Xilinx/embeddedsw

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2025.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/v_mix at xlnx_rel_v2025.1 · Xilinx/embeddedsw

The driver source code is organized into different folders. The table below shows the v_mix driver source organization.

Directory	Description

Directory	Description
src	Driver source files, make and cmakelists file
examples	Example applications that show how to use the driver features and video lock for a particular frame rate
doc	Provides the API and data structure details
data	Driver .tcl, .yaml and .mdd file

Note: the AMD embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml file (in the data folder) and CMakeLists.txt (in the src folder) are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver implementation

For a full list of features supported by this IP, see Video Mixer PG243

Features

Controller and driver features Supported:

Supports (per pixel) alpha-blending of seventeen video/graphics and logo layers video/graphics
Optional logo (in block RAM) layer with color transparency support
Layers can either be memory mapped AXI4 interface or AXI4-Stream
Provides programmable background color
Provides programmable layer position and size
Provides upscaling of layers by 1x, 2x, or 4x
Optional built-in color space conversion and chroma re-sampling
Supports RGB, YUV 444, YUV 422, YUV 420
Supports 8, 10, 12, and 16 bits per color component input and output on stream interface, 8-bit and 10-bit per color component on memory interface
Supports semi-planar memory formats next to packed memory formats
Supports spatial resolutions from 64 × 64 up to 8,192 × 4,320
Supports 8K60 in all supported device families.
Note: Performance on low power devices might be lower.
Supports Programmable CSC coefficients to support various calorimetry like BT601, BT709, and BT2020
Supports 1, 2, 4, or 8 samples per clock
Supports programmable CSC coefficient registers

Known issues and limitations

None

Example applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to examples

Examples Path:

embeddedsw/XilinxProcessorIPLib/drivers/v_mix/examples at xlnx_rel_v2025.1 · Xilinx/embeddedsw

Test/Application Name	Example source	Description

Test/Application Name	Example source	Description
xv_mix_example	v_mix/examples/src/xv_mix_example.c	This example application is built to demonstrate the functionality of the Video mixer IP and its video lock for selected resolution on ZCU102/ZCU104/ZCU106/VCK190 platforms by transferring data through primary and overlay layers.

Example application usage

xv_mix_example:

The Frame Buffer Write IP receives video data from an axi4s_stream_vid_out IP that receives video data from a streaming IP along with a timing control generated through VTC. If the axi4s_stream_video_out IP receives video data properly within timing generated by the VTC for a selected resolution, then video lock happens properly and the testcase passes. If it does not receive video properly within the timing generated by the VTC, then either video_overflow or video_underflow happens, and the test case results in failure.

Example Design Architecture

A system illustration is shown as below.


         -----------
         | Video   |
         | Timing  |---
         | Control |  |
         -----------  |
         ----------   |   ------------     ----------
         |        |   --->|   AXI4S  |     | Frame  |
         | V_Mix  |------>| to Video |---->| Buffer |
         |        |       |    OUT   |     | Write  |
         ----------       ------------     ----------

Expected Output

INFO: Test completed successfully

Change Log

2025.2

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.2 · embeddedsw/embeddedsw

2025.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.1 · embeddedsw/embeddedsw