Video Frame Buffer Write Standalone Driver

This page gives an overview of the bare-metal driver support for the Frame buffer Write standalone driver.

1 Introduction
2 Driver Sources
3 Driver implementation
4 Features
- 4.1 Controller and driver features Supported:
5 Known issues and limitations
6 Example applications
7 Links to examples
8 Example application usage
- 8.1 xv_frmbufwr_example:
  - 8.1.1 Example Design Architecture
  - 8.1.2 Expected Output
9 Change Log
- 9.1 2025.2
- 9.2 2025.1

Introduction

The AMD LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access between memory and AXI4-Stream video type target peripherals, which support the AXI4-Stream Video protocol. This IP receives video data on streaming interface from any streaming IP connected to it and transfers the data to DDR to store the received video frames.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver name	path in vitis	Parth in Github

Driver name	path in vitis	Parth in Github
v_frmbuf_wr	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/v_frmbuf_wr	embeddedsw/XilinxProcessorIPLib/drivers/v_frmbuf_wr at master · Xilinx/embeddedsw

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2025.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/v_frmbuf_wr at xlnx_rel_v2025.1 · Xilinx/embeddedsw

The driver source code is organized into different folders. The table below shows the v_frmbuf_wr driver source organization.

Directory	Description

Directory	Description
src	Driver source files, make and cmakelists file
examples	Example applications that show how to use the driver features and video lock for a particular frame rate
doc	Provides the API and data structure details
data	Driver .tcl, .yaml and .mdd file

Note: the AMD embeddedsw build flow has been changed from the 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml file (in the data folder) and CMakeLists.txt (in the src folder) are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver implementation

For a full list of features supported by this IP, see Video Frame Buffer Read / Write PG278

Features

Controller and driver features Supported:

AXI4 Compliant
Streaming Video Format support for: RGB, RGBA, YUV 4:4:4, YUVA 4:4:4, YUV 4:2:2, YUV 4:2:0
Provides programmable memory video format
Supports memory video format in raster and tile mode
Raster Mode Memory Video Format support for: RGBX8, BGRX8, YUVX8, YUYV8, UYVY8, RGBA8, BGRA8, YUVA8, RGBX10, YUVX10, Y_UV8, Y_UV8_420, RGB8, BGR8, YUV8, Y_UV10, Y_U_V8, Y_U_V10, Y_U_V12, Y_U_V8_420, Y_UV10_420, Y8, Y10, Y12
Tile Mode Memory Video Format support for: Y_U_V8, Y_U_V10, Y_U_V12, Y_UV8, Y_UV10, Y_UV12, Y_UV8_420, Y_UV10_420, _UV12_420, Y8, Y10, Y12
Supports progressive and interlaced video in Raster mode
Supports only progressive video format in tile mode
Raster Mode supports 8, 10, 12, and 16-bit per color component on stream interface and memory interface
Tile Mode supports 8, 10, and 12-bit per color component on stream and memory interface
Supports spatial resolutions from 64 × 64 up to 15360 × 8640
Supports 8K60 in all supported device families

Known issues and limitations

None

Example applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to examples

Examples Path:

embeddedsw/XilinxProcessorIPLib/drivers/v_frmbuf_wr/examples at xlnx_rel_v2025.1 · Xilinx/embeddedsw

Test/Application Name	Example source	Description

Test/Application Name	Example source	Description
xv_frmbufwr_example	v_frmbuf_wr/examples/src/xv_frmbufwr_example.c	This example application is built to demonstrate the functionality of the FrameBuffer Write IP and its video lock for selected resolution on KC705/ZCU102/ZCU104/ZCU106/VCK190 platforms.

Example application usage

xv_frmbufwr_example:

The Frame Buffer Write IP receives video data from an axi4s_stream_vid_out IP that receives video data from a streaming IP along with a timing control generated through VTC. If the axi4s_stream_video_out IP receives video data properly within timing generated by the VTC for a selected resolution, then video lock happens properly and testcase passes.

If it does not receive video properly within the timing generated by the VTC, then either video_overflow or video_underflow happens, and the test case results in failure.

Example Design Architecture

A system illustration is shown as below.


         -----------
         | Video   |
         | Timing  |---
         | Control |  |
         -----------  |
         ----------   |   ------------     ----------
         | Frame  |   --->|   AXI4S  |     | Frame  |
         | Buffer |------>| to Video |---->| Buffer |
         | READ   |       |    OUT   |     | Write  |
         ----------       ------------     ----------

Expected Output

INFO: Test completed successfully. 52/52 tests passed

Change Log

2025.2

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.2 · embeddedsw/embeddedsw

2025.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.1 · embeddedsw/embeddedsw