Migrating RTL designs from the MicroBlaze Processor to the MicroBlaze V Processor

Overview

The MicroBlaze V Processor is based on the MicroBlaze Processor. As a result, migration between the two is not difficult. For IPI based designs we offer an automation to convert MicroBlaze designs to MicroBlaze V. This automation script can also serve as a guide for those migrating RTL (IP Catalog) designs. The script can be found in a Vivado installation at data/rsb/design_assist/block/microblaze/convert.tcl

Both Lockstep and TMR RTL designs are beyond the scope of this document. They are supported in the IPI automation. RTL Lockstep and TMR designs should follow the basic steps here but care will be needed to ensure all processors have the same configuration.

MDM Migration

The MDM and MDM V IPs are almost identical in external configuration and interfaces. In most cases, the MDM V IP will be a drop-in replacement for the MDM IP. There are some parameters/generics related to use in combination with the BSCAN switch that most customers will not encounter. These can be resolved by looking at PG115 and PG428 or by creating the equivalent design in IPI and copying the applied configuration to the RTL design.

Migrating the processor IP

As with the MDM IP, migrating the processor IP is not difficult.

Ports

The vast majority of ports are identical between the two processors IPs. The trace interface on MicroBlaze V is slightly different but that is to be expected and it is too niche to cover here. There are some small changes to note.

MicroBlaze Processor	MicroBlaze V Processor	Notes

MicroBlaze Processor	MicroBlaze V Processor	Notes
Mb_Reset	-	Was internally logically OR’d with Reset, replace with external logical OR (is active low so will require some care).
MB_Halted	Halted	Renamed
MB_Error	Error	Renamed

Parameters and Generics

There are some parameter/generic differences to take into account.

These notes are here to summarize the user guide, in places where they conflict the user guide should be taken as the source of truth. The MicroBlaze Processor configuration section can be found in UG984. The MicroBlaze V configuration section can be found in UG1629.

MicroBlaze Processor	MicroBlaze V Processor	Notes

MicroBlaze Processor	MicroBlaze V Processor	Notes
C_ADDR_SIZE	C_ADDR_SIZE	If using the MMU with virtual memory in a 64-bit system, choose 39, 48 or 57 to match the RISC-V spec. If using virtual memory, copy the value from MicroBlaze.
C_AREA_OPTIMIZED	C_OPTIMIZATION	Values have the same meaning with the addition of Throughput (see UG1629) 0 = Performance 1 = Area 2 = Frequency 3 = Throughput
C_CACHE_BYTE_SIZE	C_ICACHE_BYTE_SIZE	C_DCACHE_BYTE_SIZE is equivalent between both IPs, just the ICACHE size was renamed
C_ILL_OPCODE_EXCEPTION	C_ILL_INSTR_EXCEPTION	Simple rename, values have same meaning
C_UNALIGNED_EXCEPTIONS	C_MISALIGNED_EXCEPTIONS	Simple rename
C_USE_BARREL	C_USE_BARREL	Barrel shifter is mandatory in the MicroBlaze V IP. Numeric values have different meaning 0 = Invalid 1 = Optimize for performance (same as 1 on MicroBlaze) 2 = Optimize for area (minimal config - mapped from 0 on MicroBlaze)
C_USE_DIV C_USE_HW_MUL	C_USE_MULDIV	Numeric values have different meaning 0 = No hardware multiplier (same) 1 = Normal multiplier (map nonzero C_USE_HW_MUL or C_USE_DIV here) 2 = Smart (refer to UG1629 for details)
C_USE_FPU	C_USE_FPU	Numeric values have slightly different meaning 0 = None (same) 1 = Single precision (map C_USE_FPU = 1 and C_DATA_SIZE = 32 here) 2 = Double precision (map C_USE_FPU = 1 and C_DATA_SIZE != 32 here)
C_USE_MMU	C_USE_MMU	Numeric values have slightly different meaning 0 = Machine (same) 1 = User (same and also map 2 here - 2 was Protection - refer to UG984) 3 = Supervisor (same)
G_TEMPLATE_LIST	-	No equivalent in RISC-V core, ignore
C_USE_MSR_INSTR	-	No equivalent in RISC-V standard
C_USE_PCMP_INSTR	-	No exact equivalent in RISC-V standard, consider bit manipulation
C_USE_REORDER_INSTR	-	No exact equivalent in RISC-V standard, consider bit manipulation
C_DIV_ZERO_EXCEPTION	-	No equivalent in RISC-V standard
C_FPU_EXCEPTION	-	No equivalent in RISC-V standard
C_USE_STACK_PROTECTION	-	Always supported in RISC-V

Migrating the MCS

The MCS V IP is a drop-in replacement for the MCS IP. The optimization settings for the two IP are different. Care should be taken when generating the replacement to ensure a comparable size IP is generated. The MCS IP is covered in PG116 and the MCS V is covered in PG440