HDMI 2.1 RX Subsystem standalone driver

This page gives an overview of the bare-metal driver support for the HDMI 2.1 RX subsystem standalone driver.

1 Introduction
2 Driver Sources
3 Driver implementation
4 Features
- 4.1 Controller and driver features Supported:
5 Known issues and limitations
6 Example applications
7 Links to examples
8 Example application usage
- 8.1 Pass-through applications:
  - 8.1.1 Example Design Architecture
  - 8.1.2 Expected Output
- 8.2 RX Only Applications:
  - 8.2.1 Example Design Architecture
  - 8.2.2 Expected Output
9 Change Log
- 9.1 2025.1

Introduction

The HDMI 2.1 Receiver Subsystem is a feature-rich soft IP incorporating all of the necessary logic to properly interface with PHY layers and provide HDMI decoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI 2.1 RX-related IP sub-cores and outputs them as a single IP. The subsystem receives the captured TMDS/FRL data from the video PHY layer. It then extracts the video and audio streams from the HDMI stream and converts it to video and audio streams.
The HDMI 2.1 Receiver Subsystem is a MAC subsystem which works with a HDMIPHY/GT (PHY) controller to create a video connectivity system. The HDMI 2.1 Receiver Subsystem is tightly coupled with the Xilinx HDMIPHY/GT PHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation and is also available in the Xilinx Github repository.

Driver name	Path in Vitis	Parth in Github

Driver name	Path in Vitis	Parth in Github
v_hdmirxss1	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/v_hdmirxss1	embeddedsw/XilinxProcessorIPLib/drivers/v_hdmirxss1 at master · Xilinx/embeddedsw

Note: To view the sources for a particular release, use the rel-version tag in GitHub. For example, for the 2025.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/v_hdmirxss1 at xlnx_rel_v2025.1 · Xilinx/embeddedsw

The driver source code is organized into different folders. The table below shows the v_hdmirxss1 driver source organization.

Directory	Description

Directory	Description
src	Driver source files, make and cmakelists file
examples	Example applications that show how to use the driver features
doc	Provides the API and data structure details
data	Driver .tcl, .yaml and .mdd file

Note: the AMD embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml file (in the data folder) and CMakeLists.txt file (in the src folder) are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver implementation

For a full list of features supported by this IP, see HDMI 2.1 Transmitter Subsystem PG351

Features

Controller and driver features Supported:

Dynamic support of FRL and TMDS
Dynamic support of FRL data rate (12 Gb/s @ 4 lanes, 10 Gb/s @ 4 lanes, 8 Gb/s @ 4 lanes, 6 Gb/s @ 4 lanes, 6 Gb/s @ 3 lanes, and 3 Gb/s @ 3 lanes)
Dynamic support of TMDS up to 6 Gb/s @ 3 lanes
Supports both integer and non-integer frame rates
Supports FRL training patterns LTP5, LTP6, LTP7, LTP8, No LTP, and special symbols (0xFFE and 0xFFF).
Support of resolution up to 10,240 x 4,320 @ 30 fps (in FRL mode)
Support of 8k/10kp60 YUV420 (in FRL mode)
Support of 8, 10, 12, and 16 bits per component (BPC)
Support for RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0 color formats
Support 4 and 8 pixels per clock (PPC) AXI4-Stream Video input
Supports 4 pixels per clock (PPC) Native Video and Native Video (Vectored DE) output stream
Supports L-PCM Audio up to 32 channels
High bit rate (HBR) Audio
3D audio support
Optional HDCP 2.3/1.4 decryption support
Info frames
Data Display Channel (DDC)
Cable Detect at active-High or Low polarity
Supports hot-plug detection at active-High or Low polarity
Supports HDR video transport (Dynamic Range and Mastering info frames)
- Traditional Gamma - SDR
- Traditional Gamma - HDR
- HDR 10 - SMPTE ST 2084
- Hybrid Log Gamma (HLG)
Supports enhanced gaming and media features
- Variable Refresh Rate (VRR)
- Quick Frame Transport (QFT)
- Auto Low Latency Mode (ALLM)
- Quick Media Switching (QMS)
Supports VRR
Supports Dynamic HDR
- CTA 861-H HDR dynamic metadata extended info frame
Supports HDR10+ Forum VSIF
Supports Display Stream Compression (DSC) Pass Through

Known issues and limitations

None

Example applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to examples

Examples Path:

embeddedsw/XilinxProcessorIPLib/drivers/v_hdmirxss1/examples at xlnx_rel_v2024.2 · Xilinx/embeddedsw

Test/Application Name	Example source	Description

Test/Application Name	Example source	Description
Passthrough_A53	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Transmitter and Receiver running on the Zynq UltraScale+ based ZCU102/ZCU104/ZCU106 platforms.
Passthrough_A72	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Transmitter and Receiver running on the Versal based VCK190 platform.
Passthrough_A72_VEK	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Transmitter and Receiver running on the Versal based VEK280/VEK385 platforms.
Passthrough_Microblaze	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Transmitter and Receiver running on the MicroBlaze based platforms.
Passthrough_R5	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Transmitter and Receiver running on the Zynq UltraScale+ based ZCU102/ZCU104/ZCU106 platforms where application runs R5 processor.
RxOnly_A53	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Receiver only running on the Zynq UltraScale+ based ZCU102/ZCU104/ZCU106 platforms.
RxOnly_R5	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Receiver only running on the Zynq UltraScale+ based ZCU102/ZCU104/ZCU106 platforms where application runs on R5 processor.
RxOnly_Microblaze	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to demonstrate the functionality of a Xilinx HDMI 2.1 Receiver running on the MicroBlaze based platforms.
hdcp_key_utility	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to load the HDCP keys into the EEPROM.
hdcp_key_utility_vek	xhdmi_example/PassThrough/xhdmi_example.c	This example application is built to load the HDCP keys into the EEPROM on a Versal platform.

Example application usage

Pass-through applications:

HDMI RX is to receive and lock to the incoming HDMI stream from the SOURCE. By default, HDMI TX is to transmit HDMI stream received from the SOURCE by the RX to the SINK. The application can work in 2 modes - pass-through mode and colorbar (or independent) mode. If the colorbar mode is selected (via the UART menu), a test pattern generator IP will generate a video stream according to user selection (via UART), then the HDMI TX will transmit the HDMI stream to the downstream SINK. If the HDCP (1.4, 2.2 or both) is enabled by the hardware, the application will support HDCP handling in both the HDMI TX and RX.

Example Design Architecture

A system illustration is shown as below.

         ----------     -----------     --------
         |        |     |    |    |     |      |
         | SOURCE |---->| RX | TX |---->| SINK |
         |        |     |    |    |     |      |
         ----------     -----------     --------

Expected Output

UART menu illustration

UART MENU ILLUSTRATION
------------------------
---------------------
---   MAIN MENU   ---
---------------------
i - Info
	=> Shows information about the HDMI RX stream,
	   HDMI TX stream, GT transceivers and PLL settings.
c - Change Mode
	=> Change the mode of the application from
	   pass-through to colorbar and vice-versa.
r - Resolution
	=> Change the video resolution of the colorbar.
f - Frame rate
	=> Change the frame rate of the colorbar.
d - Color depth
	=> Change the color depth of the colorbar.
s - Color space
	=> Change the color space of the colorbar.
p - Pass-through
	=> Passes the sink input to source output.
z - GT & HDMI TX/RX log
	=> Shows log information for GT & HDMI TX/RX.
e - Edid
	=> Display and set edid.
a - Audio
	=> Audio options.
v - Video
	=> Video pattern options.
h - HDCP
	=> Goto HDCP menu.\r\n
x - Debug Tools
	=> Goto Debug menu.
y - HDMI PHY Debug Menu
o - OnSemi NB7NQ621M Debug

RX Only Applications:

This example application is built to demonstrate the functionality of the Xilinx HDMI Receiver only. The HDMI RX is to receive and lock to the incoming HDMI stream from the SOURCE.

Example Design Architecture

A system illustration is shown as below.

         ----------     -----------
         |        |     |         |
         | SOURCE |---->|    RX   |
         |        |     |         |
         ----------     -----------

Expected Output

UART menu illustration

---------------------
---   MAIN MENU   ---
---------------------
i - Info
       => Shows information about the HDMI RX stream, HDMI TX stream,
          GT transceivers and PLL settings.
p - Toggle HPD
       => Toggles the HPD of HDMI RX.
l - GT PLL layout
       => Select GT transceiver PLL layout.
z - GT & HDMI TX/RX log
       => Shows log information for GT & HDMI TX/RX.
h - HDCP
       => Goto HDCP menu.

Change Log

2025.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.1 · embeddedsw/embeddedsw