Table of Contents

Introduction

In most cases a single MDM or MDM V is sufficient to debug multiple processors of the same type.  Where processor types are mixed or both MCS and IPI implementations are created some care is needed in the wiring of the debug logic.

Mixed MicroBlaze and MicroBlaze V designs

It is important that the correct MDM is used with the correct processor type. Because the DEBUG bus is identical for both MicroBlaze and MicroBlaze V, IPI allows configurations that are electrically valid but logically invalid.  They will not work because the protocol used over the bus is different.

The image below shows three configurations.

• The first is valid because each processor is using the correct MDM type.  MicroBlaze uses MDM and MicroBlaze V uses MDM V

• The second is invalid because the MDM V cannot support the debug protocol of MicroBlaze

• The third is invalid because the MDM cannot support the debug protocol of MicroBlaze V

In the valid configurations, both MDM and MDM V are set to use EXTERNAL for their BSCAN location and the Debug Bridge is configured to provide a BSCAN primitive with 2 masters.

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Mixed MicroBlaze and MicroBlaze MCS designs

In a similar manner, the debug bridge can be used to mix MicroBlaze and MicroBlaze MCS designs.  Both the MCS and MDM are set to use EXTERNAL for their BSCAN location and the Debug Bridge is configured to provide a BSCAN primitive with two masters.

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MicroBlaze V and MicroBlaze MCS V designs.

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