TPG

v_tpg@a00e0000 {
compatible = "xlnx,v-tpg-8.2" , "xlnx,v-tpg-8.0";
xlnx,max-width = <3840>;
reset-gpios = <&gpio 96 1>;
xlnx,max-height = <2160>;
xlnx,vtc = <&tpg_input_v_tc_1>;
reg = <0x0 0xa00e0000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <8>;
xlnx,ppc = <2>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
tpg_portstpg_input_v_tpg_1: ports {
#address-cells = <1>;
#size-cells = <0>;
tpg_port1tpg_input_v_tpg_1: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <2>;
tpg_outtpg_input_v_tpg_1: endpoint {
remote-endpoint = <&tpg_input_v_frmbuf_wr_0>;
};
};
tpg_port0tpg_input_v_tpg_1: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <2>;
};
};
};

tpg_input_v_tc_1: v_tc@a00d0000 {
clock-names = "clk", "s_axi_aclk";
clocks = <&misc_clk_4>, <&zynqmp_clk 71>;
compatible = "xlnx,v-tc-6.2", "xlnx,v-tc-6.1", "xlnx,bridge-v-tc-6.1";
reg = <0x0 0xa00d0000 0x0 0x10000>;
xlnx,generator ;
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

VPSS Scalar

v_proc_ss@a0080000 {
reset-gpios = <&psng0_axi_gpio_rst 3 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0080000 0x0 0x40000>;
xlnx,num-hori-taps = <6>;
xlnx,h-scaler-taps = <6>;
xlnx,topology = <0>;
compatible = "xlnx,v-proc-ss-2.3" , "xlnx,v-vpss-scaler-2.2";
xlnx,csc-enable-window = "true";
xlnx,max-width = <3840>;
xlnx,use-uram = <0>;
xlnx,v-scaler-taps = <6>;
xlnx,video-width = <8>;
xlnx,colorspace-support = <0>;
xlnx,num-vert-taps = <6>;
xlnx,pix-per-clk = <2>;
xlnx,enable-csc = "true";
xlnx,scaler-algorithm = <2>;
xlnx,v-scaler-phases = <64>;
clocks = <&misc_clk_2>, <&misc_clk_2>;
clock-names = "aclk_axis" , "aclk_ctrl";
xlnx,h-scaler-phases = <64>;
xlnx,samples-per-clk = <2>;
scaler_portspsng0_vpss_scaler: ports {
#address-cells = <1>;
#size-cells = <0>;
scaler_port1psng0_vpss_scaler: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <3>;
sca_outpsng0_vpss_scaler: endpoint {
remote-endpoint = <&psng0_v_frmbuf_wr_0psng0_vpss_scaler>;
};
};
scaler_port0psng0_vpss_scaler: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <3>;
psng0_vpss_scalerpsng0_vpss_csc: endpoint {
remote-endpoint = <&csc_outpsng0_vpss_csc>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

VPSS CSC

v_proc_ss@a0000000 {
reset-gpios = <&psng0_axi_gpio_rst 2 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0000000 0x0 0x10000>;
xlnx,h-scaler-taps = <6>;
xlnx,topology = <3>;
xlnx,csc-enable-window = "false";
compatible = "xlnx,v-proc-ss-2.3" , "xlnx,v-vpss-csc";
xlnx,max-width = <3840>;
xlnx,use-uram = <0>;
xlnx,v-scaler-taps = <6>;
xlnx,video-width = <8>;
xlnx,colorspace-support = <0>;
xlnx,scaler-algorithm = <2>;
xlnx,v-scaler-phases = <64>;
clocks = <&misc_clk_2>;
clock-names = "aclk";
xlnx,h-scaler-phases = <64>;
csc_portspsng0_vpss_csc: ports {
#address-cells = <1>;
#size-cells = <0>;
csc_port1psng0_vpss_csc: port@1 {
xlnx,video-width = <8>;
reg = <1>;
xlnx,video-format = <3>;
csc_outpsng0_vpss_csc: endpoint {
remote-endpoint = <&psng0_vpss_scalerpsng0_vpss_csc>;
};
};
csc_port0psng0_vpss_csc: port@0 {
xlnx,video-width = <8>;
reg = <0>;
xlnx,video-format = <3>;
psng0_vpss_cscpsng0_vg0: endpoint {
remote-endpoint = <&gamma_outpsng0_vg0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Demosaic

v_demosaic@a0010000 {
compatible = "xlnx,v-demosaic-1.1" , "xlnx,v-demosaic";
xlnx,max-width = <3840>;
reset-gpios = <&psng0_axi_gpio_rst 0 1>;
xlnx,max-height = <2160>;
xlnx,use-uram = <0>;
reg = <0x0 0xa0010000 0x0 0x10000>;
clocks = <&misc_clk_2>;
xlnx,s-axi-ctrl-addr-width = <6>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
demosaic_portspsng0_dm0: ports {
#address-cells = <1>;
#size-cells = <0>;
demosaic_port1psng0_dm0: port@1 {
reg = <1>;
demo_outpsng0_dm0: endpoint {
remote-endpoint = <&psng0_vg0psng0_dm0>;
};
};
demosaic_port0psng0_dm0: port@0 {
reg = <0>;
psng0_dm0csirx_0: endpoint {
remote-endpoint = <&mipi_csirx_outcsirx_0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Gamma Lut

v_gamma_lut@a0020000 {
compatible = "xlnx,v-gamma-lut-1.1" , "xlnx,v-gamma-lut";
xlnx,max-width = <3840>;
reset-gpios = <&psng0_axi_gpio_rst 1 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0020000 0x0 0x10000>;
clocks = <&misc_clk_2>;
xlnx,s-axi-ctrl-addr-width = <13>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
gamma_portspsng0_vg0: ports {
#address-cells = <1>;
#size-cells = <0>;
gamma_port1psng0_vg0: port@1 {
xlnx,video-width = <8>;
reg = <1>;
gamma_outpsng0_vg0: endpoint {
remote-endpoint = <&psng0_vpss_cscpsng0_vg0>;
};
};
gamma_port0psng0_vg0: port@0 {
xlnx,video-width = <8>;
reg = <0>;
psng0_vg0psng0_dm0: endpoint {
remote-endpoint = <&demo_outpsng0_dm0>;
};
};
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Mixer

hdmi_output_v_mix_0: v_mix@a0070000 {
reset-gpios = <&gpio 98 1>;
reg = <0x0 0xa0070000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <13>;
xlnx,ppc = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-mix-5.2" , "xlnx,mixer-3.0" , "xlnx,mixer-4.0" , "xlnx,mixer-5.0";
xlnx,num-layers = <9>;
xlnx,video-format = <0>;
interrupt-parent = <&imux>;
xlnx,bpc = <8>;
interrupts = < 0 95 4 >;
clocks = <&misc_clk_0>;
xlnx,dma-addr-width = <64>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <32>;
xlnx,max-rows = <2160>;
xlnx,max-data-width = <8>;
crtc_mixer_porthdmi_output_v_mix_0: port@0 {
reg = <0>;
mixer_crtchdmi_output_v_mix_0: endpoint {
remote-endpoint = <&hdmi_output_v_hdmi_tx_ss_0hdmi_output_v_mix_0>;
};
};
xx_mix_masterhdmi_output_v_mix_0: layer_0 {
xlnx,layer-primary;
xlnx,layer-max-height = <2160>;
xlnx,vformat = "BG24";
dmas = <&hdmi_output_v_frmbuf_rd_0 0>;
xlnx,layer-id = <0>;
xlnx,layer-streaming;
dma-names = "dma0";
xlnx,layer-max-width = <3840>;
};
xx_mix_overlay_1hdmi_output_v_mix_0: layer_1 {
xlnx,vformat = "NV12";
xlnx,layer-id = <1>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_2hdmi_output_v_mix_0: layer_2 {
xlnx,vformat = "NV12";
xlnx,layer-id = <2>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_3hdmi_output_v_mix_0: layer_3 {
xlnx,vformat = "NV12";
xlnx,layer-id = <3>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_4hdmi_output_v_mix_0: layer_4 {
xlnx,vformat = "NV12";
xlnx,layer-id = <4>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_5hdmi_output_v_mix_0: layer_5 {
xlnx,vformat = "NV12";
xlnx,layer-id = <5>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_6hdmi_output_v_mix_0: layer_6 {
xlnx,vformat = "NV12";
xlnx,layer-id = <6>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_7hdmi_output_v_mix_0: layer_7 {
xlnx,vformat = "NV12";
xlnx,layer-id = <7>;
xlnx,layer-max-width = <1920>;
};
xx_mix_overlay_8hdmi_output_v_mix_0: layer_8 {
xlnx,vformat = "NV12";
xlnx,layer-id = <8>;
xlnx,layer-max-width = <1920>;
};
xx_mix_logohdmi_output_v_mix_0: logo {
xlnx,logo-width = <64>;
xlnx,logo-height = <64>;
xlnx,layer-id = <9>;
};
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Frame Buffer Write

v_frmbuf_wr@a0070000 {
reset-gpios = <&psng0_axi_gpio_rst 4 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0070000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-frmbuf-wr-2.5" , "xlnx,axi-frmbuf-wr-v2.2";
xlnx,max-width = <3840>;
xlnx,vid-formats = "rgb888" , "bgr888" , "xbgr8888" , "xrgb8888" , "uyvy" , "y8" , "vuy888" , "xvuy8888" , "yuyv" , "nv12" , "nv16";
interrupt-parent = <&imux>;
xlnx,video-width = <8>;
interrupts = < 0 107 4 >;
clocks = <&misc_clk_2>;
xlnx,dma-align = <16>;
xlnx,dma-addr-width = <32>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <0x20>;
#dma-cells = <1>;
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Frame Buffer Read

v_frmbuf_rd@a0040000 {
reset-gpios = <&psng0_axi_gpio_rst 5 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0060000 0x0 0x10000>;
xlnx,s-axi-ctrl-addr-width = <0x7>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-frmbuf-rd-2.5" , "xlnx,axi-frmbuf-rd-v2.2";
xlnx,max-width = <3840>;
xlnx,vid-formats = "bgr888";
interrupt-parent = <&imux>;
xlnx,video-width = <8>;
interrupts = < 0 106 4 >;
clocks = <&misc_clk_2>;
xlnx,dma-align = <16>;
xlnx,dma-addr-width = <32>;
clock-names = "ap_clk";
xlnx,s-axi-ctrl-data-width = <0x20>;
#dma-cells = <1>;
}

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

Multi-scalar

v_multi_scaler_0: v_multi_scaler@a0020000 {
reset-gpios = <&axi_gpio_0 0 1>;
xlnx,max-height = <2160>;
reg = <0x0 0xa0020000 0x0 0x20000>;
xlnx,pixels-per-clock = <2>;
interrupt-names = "interrupt";
compatible = "xlnx,v-multi-scaler-1.2" , "xlnx,v-multi-scaler-v1.0";
xlnx,max-width = <3840>;
xlnx,max-chan = <8>;
xlnx,num-taps = <6>;
xlnx,vid-formats = "rgb888" , "xrgb8888" , "bgr888" , "xbgr8888" , "xbgr2101010" , "uyvy" , "y8" , "y10" , "vuy888" , "xvuy8888" , "yuvx2101010" , "yuyv" , "nv12" , "nv16" , "xv20" , "xv15";
interrupt-parent = <&imux>;
interrupts = < 0 89 4 >;
clocks = <&zynqmp_clk 71>;
xlnx,dma-addr-width = <0x40>;
clock-names = "ap_clk";
};

NA

Same as ZynqMP node.

Processing IPs are same across all platforms.

NA

NA

HDMI Video PHY

vid_phy_controller: vid_phy_controller@80050000 {
xlnx,transceiver-width = <2>;
xlnx,rx-clk-primitive = <0>;
reg = <0x00 0x80050000 0x00 0x10000>;
interrupt-names = "irq";
compatible = "xlnx,vid-phy-controller-2.2" , "xlnx,vid-phy-controller-2.1";
xlnx,rx-max-gt-line-rate = <0x5aa320>;
xlnx,hdmi-fast-switch = <1>;
interrupt-parent = <&imux>;
xlnx,nidru-refclk-sel = <4>;
xlnx,tx-protocol = <1>;
xlnx,input-pixels-per-clock = <2>;
interrupts = < 0 89 4 >;
xlnx,tx-pll-selection = <6>;
clocks = <&zynqmp_clk 71>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_4>, <&misc_clk_4>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 71>, <&misc_clk_2>;
clock-names = "drpclk" , "gtsouthrefclk0_in" , "gtsouthrefclk0_odiv2_in" , "mgtrefclk0_pad_n_in" , "mgtrefclk0_pad_p_in" , "mgtrefclk1_pad_n_in" , "mgtrefclk1_pad_p_in" , "vid_phy_axi4lite_aclk" , "vid_phy_rx_axi4s_aclk" , "vid_phy_sb_aclk" , "vid_phy_tx_axi4s_aclk";
xlnx,tx-buffer-bypass = <1>;
xlnx,nidru = <1>;
xlnx,rx-pll-selection = <0>;
xlnx,transceiver-type = <5>;
xlnx,tx-max-gt-line-rate = <0x5aa320>;
xlnx,rx-refclk-sel = <1>;
xlnx,use-gt-ch4-hdmi = <0>;
xlnx,tx-refclk-sel = <0>;
xlnx,rx-protocol = <1>;
xlnx,tx-clk-primitive = <0>;
xlnx,rx-no-of-channels = <3>;
xlnx,tx-no-of-channels = <3>;
vid_phy_controllerrxphy_lane0: vid_phy_rx_axi4s_ch0v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllerrxphy_lane1: vid_phy_rx_axi4s_ch1v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllerrxphy_lane2: vid_phy_rx_axi4s_ch2v_hdmi_rx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane0: vid_phy_tx_axi4s_ch0v_hdmi_tx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane1: vid_phy_tx_axi4s_ch1v_hdmi_tx_ss {
#phy-cells = <4>;
};
vid_phy_controllertxphy_lane2: vid_phy_tx_axi4s_ch2v_hdmi_tx_ss {
#phy-cells = <4>;
};
};

&zynq_us_ss_0_fmch_axi_iic {
/* Si5324 i2c clock generator /
si5324: clock-generator@68 {
compatible = "silabs,si5324";
reg = <0x68>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/ input clock(s); the XTAL is hard-wired on the ZCU102 board /
clocks = <&refhdmi>;
clock-names = "xtal";
/ output clocks /
clk0 {
reg = <0>;
/ HDMI TX reference clock output frequency */
clock-frequency = <27000000>;
};

};