Window Watchdog

Introduction

This page describes the Window watchdog driver which is available in mainline and Xilinx Linux distribution as drivers/watchdog/xilinx_wwdt.c

HW IP Features

The window watchdog timer mode is enabled by the Enable_and_Status [WEN] bit. The two windowed watchdog timer modes are basic and Q&A, and the mode is selected by the Funct_Ctrl [WM] bit.

In both windowed modes, the timer starts with the first window defined by a 32-bit field in the First_Wind register. The first window is considered the closed window. This is followed by a second window defined by another 32-bit field in the Second_Wind register. The second window is considered the open window. The protocol to keep the watchdog timer operating correctly depends on the window mode and the optional features that are enabled. In the simplest mode, the timer is restarted during the open window time.

Normally, if software tries to restart the timer before the open window time period, a bad event occurs, and the timer can generate a system interrupt or reset.

The Q&A token window mode requires the system software to write three one-byte responses during the first window (closed window) and a one-byte write in the second window (open window). The value of the token responses are based on the seed, feedback, and an answer count value. The seed and feedback values are programmed by software. The answer count value increments by one for each token response.

The two window timer modes include:

  • Windowed Basic Mode
  • Windowed Q&A Mode

For more details refer Versal TRM.

Features supported in driver

  • Supports only Windowed Basic Mode.
  • The maximum timeout supported by the IP is dependent on the clock frequency. The driver supports window mode when timeout is less than or equal to maximum timeout supported by IP. 
  • For example, for 150MHz, the maximum timeout supported by IP is 57sec. For timeout<=57sec, the driver supports window watchdog mode
  • If the timeout provided by the user exceeds the maximum timeout supported by the IP (ex: for 150MHz, timeout > 57sec), the driver supports the higher timeouts but uses only the open window and acts as a generic watchdog.

Known Issues and Limitations

  • In Windowed Basic mode, the current driver does not support timeouts larger than UINT_MAX / 1000.
  • In Windowed Basic mode, the current driver supports only for clock frequency greater than 1MHz
  • The current driver does not support Windowed Q&A mode.

Kernel Configuration

The following config options should be enabled in order to build the xilinx window watchdog driver:
CONFIG_XILINX_WINDOW_WATCHDOG
CONFIG_WATCHDOG
│ Symbol: XILINX_WINDOW_WATCHDOG [=y] │ 
│ Type : tristate │ 
│ Defined at drivers/watchdog/Kconfig:307 │ 
│ Prompt: Xilinx window watchdog timer │ 
│ Depends on: WATCHDOG [=y] && HAS_IOMEM [=y] && (ARM64 [=y] || COMPILE_TEST [=n]) │ 
│ Location: │ 
│ -> Device Drivers │ 
│ -> Watchdog Timer Support (WATCHDOG [=y]) │ 
│ (1) -> Xilinx window watchdog timer (XILINX_WINDOW_WATCHDOG [=y]) │ 
│ Selects: WATCHDOG_CORE [=y] 


Devicetree

For more details, please refer
Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml
Example:
watchdog@fd4d0000 {
	compatible = "xlnx,versal-wwdt";
	reg = <0xfd4d0000 0x10000>;
	clocks = <&clock25>;
	timeout-sec = <30>;
};

Test procedure

Input to the driver:

  1. User can modify the timeout the device-tree.
  2. User can also provide the timeout and close-window percentage from user-space as module parameters.

Xilinx Window Watchdog driver testing from userspace:

  1. Start the watchdog timer, if there is no ping till the timeout seconds, it will generate reset interrupt at timeout seconds

    echo s > /dev/watchdog
    vck190
    [    9.322914] Xilinx window watchdog fd4d0000.watchdog: Xilinx window watchdog Timer with timeout 20s
    
    xilinx-vck190-20241:/home/petalinux# echo s > /dev/watchdog 
    [  100.667738] watchdog: watchdog0: nowayout prevents watchdog being stopped!
    [  100.674655] watchdog: watchdog0: watchdog did not stop!
    
    
    [172464.626]PMC EAM ERR1: 0x200
    [172464.676]PSM EAM Interrupt: ERR1: 0x0 ERR2: 0x2 
    [172469.164]Received EAM error. ErrorNodeId: 0x2810C000, Register Mask: 0x2. The corresponding Error ID: 0x61
  2. Ping test using watchdog-test app

    xilinx-vck190-20241:/home/petalinux#./watchdog-test 

    Ping every 1 sec.

    vck190
    [    9.322914] Xilinx window watchdog fd4d0000.watchdog: Xilinx window watchdog Timer with timeout 20s
    
    xilinx-vck190-20241:/home/petalinux# ./watchdog-test 
    Watchdog Ticking Away!
    ................................................................................

Note: For Watchdog timer (WDT) reset-on-timeout, refer https://adaptivesupport.amd.com/s/article/1229556?language=en_US 

Mainline Status
  • This driver is currently in sync with the mainline kernel

Change Log

  • 2024.2

    • Summary
      • watchdog: xilinx_wwdt: Calculate max_hw_heartbeat_ms using clock frequency
      • Revert "watchdog: xilinx_wwdt: Add check for timeout limit and set maximum value if exceeded"
    • Commits
      •  8edeb3c xilinx_wwdt: Calculate max_hw_heartbeat_ms using clock frequency
      • 1fcf5e9 xilinx_wwdt: Add check for timeout limit and set maximum value if exceeded
  • 2024.1

    • Summary
      • watchdog: xilinx_wwdt: Add check for timeout limit and set maximum value if exceeded
      • watchdog: xilinx_wwdt: Use div_u64() in xilinx_wwdt_start()
      • watchdog: Explicitly include correct DT includes
    • Commits
      • 3860676 watchdog: xilinx_wwdt: Add check for timeout limit and set maximum value if exceeded 
      • 98334dc watchdog: xilinx_wwdt: Use div_u64() in xilinx_wwdt_start() 
      • cc85f87 watchdog: Explicitly include correct DT includes
  • 2023.2

    • Summary
      • watchdog: xilinx_wwdt: Add "xlnx,versal-wwdt-1.0" compatible
      • watchdog: xilinx_wwdt: Add Versal window watchdog support
    • Commits
      • 6d768de watchdog: xilinx_wwdt: Add "xlnx,versal-wwdt-1.0" compatible
      • f1b7739 watchdog: xilinx_wwdt: Add Versal window watchdog support


Related Links

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy