1 Introduction
2 Driver Sources
3 Driver Implementation
- 3.1 Features
  - 3.1.1 Controller/Driver features supported
- 3.2 Known Issues and Limitations
4 Example Applications
- 4.1 Links to Examples
- 4.2 Example Application Usage
  - 4.2.1 resetps example
5 Example Design Architecture
6 Performance
7 Change Log
8 Related Links

Introduction

This page provides details related to the standalone resetps driver. This driver supports resetps Zynq Ultrascale+ MPSoC . For more information, please refer to Clocking chapter in ), ZynqMP TRM (UG1085) .

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github

Driver Name	Path in Vitis	Path in Github
resetps	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/resetps	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/resetps

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/resetps

The driver source code is organized into different folders. The table below shows the resetps driver source organization.

Directory	Description

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl, .mdd and .yaml file
examples	Example applications that show how to use the driver features
src	Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to Clocks and Resets Chapter in ZynqMP TRM (UG1085) .

Features

Controller/Driver features supported

Reset the PS peripherals

Known Issues and Limitations

The following features are not supported:
- The PL reset is not supported

Example Applications

Resetps driver example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/resetps

Test Name	Example Source	Description

Test Name	Example Source	Description
Resetps example	https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/resetps/examples/xresetps_example.c	Resets a list of peripherals provided by PeriList .

Example Application Usage

resetps example

Resetps example asserts and deasserts the reset to set of peripherals provided. .

Expected Output

Zynq MP First Stage Boot Loader

Release 2024.1   May 21 2024  -  10:36:43
Reset Example Test
Reset passed for Reset ID 67
Reset passed for Reset ID 41
Reset passed for Reset ID 39
Reset passed for Reset ID 32
Reset passed for Reset ID 42
Successfully ran Reset Test

Example Design Architecture

NA

Performance

NA

Change Log

2024.1

embeddedsw/doc/ChangeLog at xilinx_v2024.1 · Xilinx/embeddedsw

2023.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.2/doc/ChangeLog#L595

Xilinx Wiki

Standalone Resetps Driver