1 Introduction
2 Driver Sources
3 Driver Implementation
- 3.1 Features
  - 3.1.1 Controller/Driver features supported
- 3.2 Known Issues and Limitations
4 Example Applications
- 4.1 Links to Examples
- 4.2 Example Application Usage
  - 4.2.1 clockps example
5 Example Design Architecture
6 Performance
7 Change Log
8 Related Links

Introduction

This page provides details related to the standalone clockps driver. This driver supportsclockps Zynq Ultrascale+ MPSoC . For more information, please refer to Clocking chapter in ), ZynqMP TRM (UG1085) .

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github

Driver Name	Path in Vitis	Path in Github
clockps	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/clockps	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clockps

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2021.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/clockps

The driver source code is organized into different folders. The table below shows the clockps driver source organization.

Directory	Description

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl, .mdd and .yaml file
examples	Example applications that show how to use the driver features
src	Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to ClockingChapter in ZynqMP TRM (UG1085) .

Features

Controller/Driver features supported

Clock enable and disable
Setting Rate.

Known Issues and Limitations

The following features are not supported:
- External clocks

Example Applications

Clockps driver example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clockps

Test Name	Example Source	Description

Test Name	Example Source	Description
Clockps I2C example	https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/clockps/examples/xclockps_i2c_example.c	As an example the I2C clocks are enabled and rate is set.

Example Application Usage

clockps example

Clockps example enables and disables the I2C clocks as an example.

Expected Output

Zynq MP First Stage Boot Loader

Release 2024.1   May 21 2024  -  12:15:43
Clock Example Test
I2C0_REF Operating Rate = 99990000
Setting rate for I2C0_REF to Rate = 1428428
I2C0_REF Operating Rate = 1428429
Setting rate for I2C0_REF to Rate = 33330000
I2C0_REF Operating Rate = 33330000
Successfully ran Clock Test

Example Design Architecture

NA

Performance

NA

Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L1942

2023.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.2/doc/ChangeLog#L694