The Zynq® UltraScale+™ RFSoC ZCU216 kit and RF DC Evaluation Tool includes everything needed for quick out of box evaluation of the excellent Gen 3 DAC/ADC performance. The RF DC Evaluation Tool provides the perfect SW platform for easy generation and acquisition of RF signals to quickly get you moving toward the prototype/development stage. For more information on the ZCU216 boards and its associated add-on cards (XM650, XM655, CLK104), please see https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/769228974
RF Data Converter Evaluation Tool Software Download
Under the Additional Tools, IP and Resources tab, Click on “Package Download” to download the software, then unzip the install package in your desired location.
NOTE: An administrator account on your laptop/PC might be necessary to complete the install.
Click next and select the options you desire such as the install location.
If you have a previous version of the RF DC Evaluation tool, it is a recommended to install the new version in a different location.
Navigate to \Distribution_RF_DC_Evaluation_UI\Externals
2. Copy \Distribution_RF_DC_Evaluation_UI\Externals\image\216 contents onto a micro-SD card formatted to the FAT standard.
3. Insert the micro-SD card into the ZCU216.
Assemble the ZCU216 (main board) with the CLK-104 clocking board as shown.
Carefully attach the add-on card extender board with the screws provided.
Example: Loopback between DAC Tile 0: DAC 0 and ADC tile 0: ADC 0.
Connect the HC2-to-SMA cables to locations JHC1 and JHC5 and tighten with the hex key provided.
Connect pins 0 and 1 of JHC1 and JHC5 to the 10MHz-to-1GHz baluns on the XM655/616B as show below. We will generate a single tone at 200MHz hence the choice of baluns 10MHz-1GHz. An additional Low Pass Filter (2500MHz) can be added to suppress the DAC image. For other waveforms, a different choice of baluns and additional filters provided can be used.
Use the cable provided to interconnect J13 and J17 and complete the loop-back as shown:
Connect the power and network cables.
The RF DC Evaluation tool uses Windows OS Automatic Private IP Addressing (APIPA) feature so that you only have to connect a network cable between the board and host computer.
Change DIP switch SW2 to SD boot mode. The ZCU216 will have all Jumpers and Switch Settings in their default position when unboxed. If necessary, you can refer to “Default Jumper and Switch Settings” in the ZCU216 Board User Guide to check.
Note the location of power switch.
Note the location of DIP switch SW2.
Connect to a power source and turn on the board power using switch SW15.
The board powers on and boots from the SD card using the programmed images.
The DONE and INIT_B LEDs will turn green
It takes approximately 60s for the operating system to fully boot and for the embedded software to start.
Start the Evaluation tool
Double-click on the “RF Data Converter Evaluation User Interface” shortcut created during the install process, or from the install directory double-click on RF_DC_Evaluation_UI.exe.
If the embedded software on the ZU216 is ready, then the evaluation application will quickly establish communications and start to read the device configuration.
When device configuration reading is complete, you will see a screen similar to the following;
The right-hand side of the window is used to display information about selected blocks, for example a single-click on “ADC Tile 0” will show;
DAC Signal Generation
Double-click on DAC Tile 0.
Double-click on DAC channel 0, (avoiding the selectable sub-blocks).
Click on "Generate" to start signal generation by the DAC.
ADC Signal Acquisition
Double-click on ADC tile 0.
Double-click on ADC 0, (avoiding the selectable sub-blocks).
Click “Acquire” to see the signal that has been looped back from DAC Tile 0: DAC 0.
Select a suitable windowing if it is necessary to reduce the distortion of the spectrum due to sampling incoherence.
Check configuration of external clocks from the CLK-104.
You can check this with single-click on “Clock Settings” to see;
Checking the Clock Distribution Configuration
Click on "Clock Distribution".
You can check that the clock distribution matches the following default setting:
For improved performance, power consumption reduction, and avoid windowing, we can use the settings below which distribute the output of the ADC and DAC PLL. Please note that the ADC and DAC sampling rate must be an integer multiple of the reference clock input when using the internal PLL.