Zynq UltraScale+ MPSoC VCU TRD 2022.1 - Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display
This page provides all the information related to Design Module 7 - VCU TRD Xilinx low latency(LLP2) PS DDR NV12 HDMI Audio Video Capture and Display design.
Table of Contents
1 Overview
This module enables capture of video and audio data from an HDMI-Rx subsystem implemented in the PL. The video and audio data can be displayed through the HDMI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video and audio through an Ethernet interface at ultra-low latencies using Sync IP. This module supports four video streams using AXI broadcaster at capture side and mixer at display side for NV12 pixel format. It also supports single-stream audio.
The VCU encoder and decoder operate in slice mode. An input frame is divided into multiple slices (8 or 16) horizontally. The encoder generates a slice_done interrupt at every end of the slice. Generated NAL unit data can be passed to a downstream element immediately without waiting for the frame_done interrupt. The VCU decoder also starts processing data as soon as one slice of data is ready in its circular buffer instead of waiting for complete frame data. The Sync IP does an AXI transaction-level tracking so that the producer and consumer can be synchronized at the granularity of AXI transactions instead of granularity at the video buffer level. Sync IP is responsible for synchronizing buffers between Capture DMA and VCU encoder as both work on same buffer.
The capture element (FB write DMA) writes video buffers in raster-scan order. SyncIP monitors the buffer level while the capture element is writing into DRAM and allows the encoder to read input buffer data if the requested data is already written by DMA, otherwise it blocks the encoder until DMA completes its writes. On the decoder side, the VCU decoder writes decoded video buffer data into DRAM in block-raster scan order and displays reads data in raster-scan order. To avoid display under-run problems, software ensures a phase difference of "~frame_period/2", so that decoder is ahead compare to display.
This design supports the following video interfaces:
Sources:
HDMI-Rx capture pipeline implemented in the PS.
Stream-In from network or internet.
Sinks:
HDMI-Tx display pipeline implemented in the PS.
VCU Codec:
Video Encode/Decode capability using VCU hard block in PS
AVC/HEVC encoding
Encoder/decoder parameter configuration.
Video format:
NV12
Supported Resolutions:
The table below provides the supported resolution for this design.
Resolution | Command Line | |
Single Stream | Multi-stream | |
4kp60 | √ | NA |
4kp30 | √ | √ (Max 2) |
1080p60 | √ | √ (Max 4 for encoder) (Max 2 for decoder) |
√ - Supported
NA – Not applicable
x – Not supported
When using Low Latency mode (LLP1/LLP2), The encoder and decoder are limited by the number of internal cores. The encoder has a maximum of four streams and the decoder has a maximum of two streams.
The below table gives information about the features supported in this design.
Pipeline | Video Input | Audio Input | Video Format | Video Output | Audio Output | Resolution | VCU codec |
---|---|---|---|---|---|---|---|
Serial pipeline | HDMI-Rx | HDMI-Rx | NV12 | HDMI-Tx | HDMI-Tx | 4kp60/4kp30/1080p60 | HEVC/AVC |
Stream-Out pipeline | HDMI-Rx | HDMI-Rx | NV12 | Stream-Out | Stream-Out | 4kp60/4kp30/1080p60 | HEVC/AVC |
Stream-in pipeline | Stream-In | Stream-In | NV12 | HDMI-Tx | HDMI-Tx | 4kp60/4kp30/1080p60 | HEVC/AVC |
The below figure shows the Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display design hardware block diagram.
The below figure shows the Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display design software block diagram.
1.1 Board Setup
Refer to the below link for Board Setup
1.2 Run Flow
The TRD package is released with the source code, Vivado project, PetaLinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME
- which is the home directory.
Refer to Section 4.1 : Download the TRD of the
Zynq UltraScale+ MPSoC VCU TRD 2022.1
wiki page to download all TRD contents.
TRD package contents are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_llp2_hdmi_nv12/
to the FAT32 formatted SD card directory.
rdf0428-zcu106-vcu-trd-2022-1/
├── apu
│ └── vcu_petalinux_bsp
├── images
│ ├── vcu_audio
│ ├── vcu_llp2_hdmi_nv12
│ ├── vcu_llp2_hlg_sdi
│ ├── vcu_llp2_plddr_hdmi
│ ├── vcu_multistream_nv12
│ ├── vcu_plddrv1_hdr10_hdmi
│ ├── vcu_plddrv2_hdr10_hdmi
│ └── vcu_yuv444
├── pl
│ ├── constrs
│ ├── designs
│ ├── prebuild
│ ├── README.md
│ └── srcs
├── README.txt
└── zcu106_vcu_trd_sources_and_licenses.tar.gz
16 directories, 3 files
TRD package contents specific to Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display design are placed in the following directory structure.
rdf0428-zcu106-vcu-trd-2022-1
├── apu
│ └── vcu_petalinux_bsp
│ └── xilinx-vcu-zcu106-v2022.1-final.bsp
├── images
│ ├── vcu_llp2_hdmi_nv12
│ │ ├── autostart.sh
│ │ ├── BOOT.BIN
│ │ ├── bootfiles/
│ │ ├── boot.scr
│ │ ├── config/
│ │ ├── Image
│ │ ├── rootfs.cpio.gz.u-boot
│ │ ├── system.dtb
│ │ └── vcu/
├── pl
│ ├── constrs/
│ ├── designs
│ │ ├── zcu106_llp2_audio_nv12/
│ ├── prebuild
│ │ ├── zcu106_llp2_audio_nv12/
│ ├── README.md
│ └── srcs
└── README.txt
└── zcu106_vcu_trd_sources_and_licenses.tar.gz
Configuration files(input.cfg) for various resolutions are placed in the following directory structure in /media/card
.
The single streams configs (
1-1080p60, 1-4kp30 and 1-4kp60
) support Audio and Video both.As llp2 stream-in is not supported with vcu-gst-app, we have added sample shell scripts containing relevant GStreamer commands for all Stream-in use-cases. User can modify the scripts as per convenience, or can directly use GStreamer pipelines provided in this wiki page.
For 4x1080p60 display use-case, we have added sample shell scripts containing relevant GStreamer commands for all Display use-cases. User can modify the scripts as per convenience, or can directly use GStreamer pipelines provided in this wiki page.
config/
├── 1-1080p60
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
├── 1-4kp30
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
├── 1-4kp60
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
├── 2-1080p60
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
├── 2-4kp30
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
├── 4-1080p60
│ ├── Display
│ ├── Stream-in
│ └── Stream-out
└── input.cfg
24 directories, 1 file
1.2.1 GStreamer Application (vcu_gst_app)
The vcu_gst_app is a command-line multi-threaded Linux application. The command-line application requires an input configuration file (input.cfg) to be provided in plain text.
Run below modetest command to set CRTC configurations for 4kp60:
Run below modetest command to set CRTC configurations for 4kp30:
Execution of the application is shown below:
Example:
Make sure HDMI-Rx should be configured to 4kp60 mode while running below example pipelines.
Low latency(LLP1/LLP2) video and audio+video stream-in pipelines are not supported in vcu_gst_app.
The vcu_gst_app uses RTP+RTCP streaming and opus encoder for LLP1/LLP2 audio+video stream-out use-cases.
All single-stream serial/streaming pipelines have audio configuration ON by default. To execute only display pipeline, change the
Audio Enable
property toFALSE
in the configuration file.
4kp60 NV12 HEVC_25Mbps ultra low-latency(LLP2) audio+video serial pipeline execution.
4kp60 NV12 HEVC_25Mbps ultra low-latency(LLP2) stream-out pipeline execution.
4kp60 NV12 HEVC ultra-low-latency(LLP2) video stream-in pipeline execution.
OR
4kp60 NV12 HEVC ultra-low-latency(LLP2) audio+video stream-in pipeline execution. where 192.168.25.90
is the server’s IP address.
OR
For LLP1/LLP2 Multi-stream HEVC serial and stream-out use-cases (2-4kp30, 2-1080p60, 4-1080p60), use ENC_EXTRA_OP_BUFFERS=10
variable before vcu_gst_app command. The sample pipeline is given below:
To measure the latency of the pipeline, run the below command. The latency data is huge, so dump it to a file.
Refer to the below link for detailed run flow steps
1.3 Build Flow
Refer to the below link for detailed build flow steps
2 Other Information
2.1 Known Issues
For PetaLinux related known issues please Refer to: PetaLinux 2022.1 - Product Update Release Notes and Known Issues
For VCU related known issues please Refer to AR# 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues and Xilinx Zynq UltraScale+ MPSoC Video Codec Unit.
To reduce performance issues with llp2 4x serial pipelines, please refer to IRQ Balancing in PG252.
2.2 Limitations
For PetaLinux related limitations please refer to: PetaLinux 2022.1 - Product Update Release Notes and Known Issues
For VCU related limitations please refer to Answer Record 76600: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues, Xilinx Zynq UltraScale+ MPSoC Video Codec Unit and PG252.
2.3 Optimum VCU Encoder parameters for use-cases
Video streaming:
Video streaming use-case requires very stable bitrate graph for all pictures.
It is good to avoid periodic large Intra pictures during the encoding session
Low-latency rate control (hardware RC) is the preferred control-rate for video streaming, it tries to maintain equal amount frame sizes for all pictures.
Good to avoid periodic Intra frames instead use low-delay-p (IPPPPP…)
VBR is not a preferred mode of streaming.
Performance: AVC Encoder settings:
It is preferred to use 8 slices only for better AVC encoder performance.
AVC standard does not support Tile mode processing which results in the processing of MB rows sequentially for entropy coding.
Quality: Low bitrate AVC encoding:
Enable profile=high and use qp-mode=auto for low-bitrate encoding use-cases.