Sysmonpsv (Sysmon for Versal)

This page gives an overview of sysmonpsu driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents

Introduction

 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

Driver Name

Path in Vitis

Path in Github

axidma

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axidma_<version>

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma

 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: 

https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axidma

The driver source code is organized into different folders.  The table below shows the <Driver Name> driver source organization. 

Directory

Description

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer to the <link to IP Product Page>.  

Features

The <IP Name> Standalone driver supports the following features: 

  • Feature 1

  • Feature 2

  • Feature 3

Known Issues and Limitations

The following is a list of known limitations of the driver and features of the IP that are not currently implemented: 

  • Feature 1

  • Feature 3

  • AR #

  • Bug Info

  • etc

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
 https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axidma/examples

Test Name

Example Source

Description

Test Name

Example Source

Description

Self Test

xaxidma_example_selftest.c

This example does a basic reset of the core and checks core is coming out of reset or not.

Scatter Gather DMA with Interrupts

xaxidma_example_sg_intr.c

This example demonstrates how to transfer packets in interrupt mode when the core is configured in Scatter Gather Mode.

Scatter Gather DMA with Polling

xaxidma_example_sg_poll.c

This example demonstrates how to transfer packets in the scatter gather polled mode.

Simple DMA with Interrupt

xaxidma_example_simple_intr.c

This example demonstrates how to transfer packets in interrupt mode when the core is configured in Simple DMA Mode.

Simple DMA with Polling

xaxidma_example_simple_poll.c

This example demonstrates how to transfer packets in the polled mode when the core is configured in Simple DMA Mode.

Multi-Channel SGDMA with Interrupts

xaxidma_multichan_sg_intr.c

This example demonstrates how to packets in interrupt mode when the core is configured in Multi-Channel Mode.

SGDMA Multi-Packet Polled Mode

xaxidma_poll_multi_pkts.c

This example demonstrates how to transfer multiple packets in the polled mode when the core is configured in Scatter Gather Mode.

Example Application Usage

Self Test

This example does a basic reset of the core and checks core is coming out of reset or not.

Expected Output

This is what should be on the screen Pass or Fail etc.

Scatter Gather DMA with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in Scatter Gather Mode.

Expected Output

This is what should be on the screen Pass or Fail etc.

Scatter Gather DMA with Polling

This example demonstrates how to transfer packets in the scatter gather polled mode.

Expected Output

This is what should be on the screen Pass or Fail etc.

Example Design Architecture