2017.1 Linux and DTG Release Notes

Linux Feature Changes

Module Name	Driver Location	Feature Changes	Link
Linux kernel	Linux kernel source	Upgrade to 4.9	https://kernelnewbies.org/Linux_4.9
ZynqMP AMS	drivers/iio/adc/xilinx-ams.c	Added new AMS driver	http://www.wiki.xilinx.com/ZynqMP+AMS
Zynq, ZynqMP Ethernet, macb	drivers/net/ethernet/cadence/macb.c	PM support was added. This includes adding runtime PM support, context loss management, cleanup of clock enable/disable paths and updating mdio access functions. Please note that ethernet does not work after a suspend-resume yet and required interface to be brought down and up manually.	http://www.wiki.xilinx.com/Macb+Driver
Zynq/Zynq Ultrascale+ MPSOC/Microblaze Axi Ethernet	drivers/net/ethernet/xilinx/xilinx_axienet_main.c drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c drivers/net/ethernet/xilinx/xilinx_axienet.h	Added Support for 10G/25G MAC Added 1588 Support for 10G/25G MAC Added Support for 2.5G MAC Added Clock Support in the driver Fixed issues with the without DRE DMA based design on zynqMP SOC Fixed bug in the rx reject interrupt handling.	http://www.wiki.xilinx.com/Linux+AXI+Ethernet+driver
Platform: Zynq Ultrascale+ MPSOC IP: ZynqMP DMA	drivers/dma/xilinx/zynqmp_dma.c	Added Runtime PM support Fixed issues with the overflow interrupt.	http://www.wiki.xilinx.com/Zynqmp+DMA
Clock Framework	drivers/clk/zynqmp/clkc.c drivers/clk/zynqmp/clk-mux-zynqmp.c drivers/clk/zynqmp/pll.c drivers/clk/zynqmp/clk-gate-zynqmp.c drivers/clk/zynqmp/divider.c	dp sharing the parent (VPLL).A warn is added to check for the same. Sets the set rate parent for video clocks. Fractional mode support is enabled.	http://www.wiki.xilinx.com/Common+Clock+Framework
Platform: Zynq Ultrascale+ MPSOC USB	drivers/usb/dwc3/	Added USB 2.0 OTG driver Added CCI (Cache Coherent Interconnect) support for USB Fixed the logic for enabling host bulk streaming support	http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
Platform: Zynq Ultrascale+ MPSOC SATA	drivers/ata/ahci_ceva.c	Added CCI support in SATA if "dma-coherent" flag is enabled in device-tree node	http://www.wiki.xilinx.com/SATA
Zynq Ultrascale+ MPSOC	drivers/spi/spi-zynqmp-gqspi.c	Added Runtime PM support Updated the driver to support both IO and DMA (either IO or DMA)	http://www.wiki.xilinx.com/Linux+ZynqMP+GQSPI+Driver
Zynq/Zynq Ultrascale+ MPSOC/Microblaze	drivers/spi/spi-xilinx.c	Add clock adaptation	www.wiki.xilinx.com/Linux+SPI+Driver
Zynq Ultrascale+ MPSOC	drivers/mtd/nand/arasan_nand.c	Update Arasan Nand flash controller, as per latest kernel layer update	http://www.wiki.xilinx.com/NAND
Zynq	drivers/mtd/nand/pl35x_nand.c	Update Nand SMC flash controller, as per latest kernel layer update	www.wiki.xilinx.com/Zynq+Pl353+SMC+and+NAND+drivers
ZynqMP SD	drivers/mmc/host/sdhci-of-arasan.c	Add pinctrl support to the driver. By adding this driver should be able to handle optional pinctrl setting.	http://www.wiki.xilinx.com/SD+controller
ZynqMp Fpga Manager	drivers/fpga/zynqmp-fpga.c	Adopted Encrypted BitStream loading support for Xilinx ZynqMp. Adopted Authenticated BitStream loading support for Xilinx.	http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming#x-Programming%20the%20PL%20through%20Linux
Zynq/ Zynq Ultrascale+ MPSoC GPIO	drivers/gpio/gpio-zynq.c	Added support for suspend resume	http://www.wiki.xilinx.com/Linux+GPIO+Driver
axi_gpio	drivers/gpio/gpio-xilinx.c	Added clock adaptation support	http://www.wiki.xilinx.com/AXI+GPIO
ZynqMP pinctrl	drivers/pinctrl/pinctrl-zynqmp.c	Added pin controller driver >	http://www.wiki.xilinx.com/ZynqMP+Linux+Pin+Controller+Driver
Zynq/ZynqMp I2C Controller	drivers/i2c/busses/i2c-cadence.c	Added bus Recovery support	http://www.wiki.xilinx.com/Cadence+I2C+Driver
axi_timebase_wdt	drivers/watchdog/of_xilinx_wdt.c	Added clock adaptation support.	http://www.wiki.xilinx.com/Axi+Watchdog
Xilinx DRM KMS	drivers/gpu/drm/xilinx/*	Add a MIPI DSI driver Support clocking through PS CCF Support busid Support suspend / resume	http://www.wiki.xilinx.com/Xilinx+DRM+KMS+driver

DTG Feature Changes

Module Name	Feature Changes	Link
Generic	Add board dtsi files All board level info will be generated by DTG Added CCI support to generate dma-coherent Boot args updated (replaced earlyprintk with earlycon) Added slice support Added ccf dtsi (zynqmp-clk-ccf.dtsi)	http://www.wiki.xilinx.com/Build+Device+Tree+Blob
Ams	Added new driver
Axi Ethernet	Added 10G/25G MAC support
Display Port	Added new driver
Xadc	Added new compatible string i.e "xlnx,axi-xadc-1.00.a" Added new properties xlnx,external-mux and xlnx,external-mux-channel
Vcu	Added new driver
Pr_decoupler	Added new driver
RM	Add RM support as fpga_region for zynq link to devcfg

Linux Bug Fixes

Module Name	Driver Location	Bug Fixes	Link
Zynq, ZynqMP Ethernet, macb	drivers/net/ethernet/cadence/macb.c	Fix ptp time adjustment for large negative delta Release spinlock before calling ptp_clock_unregister Correct TSU_CAPS mask Fix PHY reset via GPIO and only call GPIO functions if there is a valid GPIO	http://www.wiki.xilinx.com/Macb+Driver
Phy, DP83867	driver/net/phy/dp83867.c	Added SW workaround for link instability on DP83867	NA
Clock Framework	drivers/clk/zynqmp/	Fixed watchdog clock source	http://www.wiki.xilinx.com/Common+Clock+Framework
Zynq/Zynq Ultrascale+ MPSOC/Microblaze AXI DMA/CDMA/VDMA	drivers/dma/xilinx/xilinx_dma.c	AXI DMA Fixed race condition in the driver for multiple descriptor scenario for axidma. Added channel idle checks across the driver. AXI CDMA Fixed bug in multiple frame stores scenario in vdma Added channel idle checks across the driver. AXI VDMA Added channel idle checks across the driver.	http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
Zynq/Zynq Ultrascale+ MPSOC	drivers/spi/spi-cadence.c	Add support for context loss	http://www.wiki.xilinx.com/SPI+Zynq+driver
Zynq Ultrascale+ MPSOC	drivers/mtd/nand/arasan_nand.c	Change ref clk in SDR modes 2 to 5 to less than 90MHz	http://www.wiki.xilinx.com/NAND
Zynq Ultrascale+ MPSOC	drivers/edac/zynqmp_ocm_edac.c	don't hardcode edac device index	NA
Zynq ADC, axi_xadc	drivers/iio/adc/xilinx-xadc-core.c	Fix for the external channel read issue by reading the 'reg' property from the devicetree before selecting the adc channel.	http://www.wiki.xilinx.com/xadc
Zynq Ultrascale+ MPSOC USB	drivers/usb/dwc3/	Assigned dwc3 archdata to xhci dev to avaiod empty dma ops Added U3 suspend quirk for silicon revisions > 3.0 for fixing ep configuration error Programme GFLADJ register based on the value from dts Changed dwc3-of-simple.c file for configuring PIPE3 signals as part of phy_init Corrected f_hid gadget Correct the logic for ep ring caching in xhci Added support for Light reset instead of HARD reset if OTG is enabled	http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
Zynq Ultrascale+ MPSOC SATA	drivers/ata/ahci_ceva.c	Corrected the sequence of AXI bus configuration register programming	http://www.wiki.xilinx.com/SATA
Zynq Ultrascale+ MPSOC SIOU/SERDES	drivers/phy/phy-zynqmp.c	Removed tx_termination_fix flag and added the calibration fix based on the silicon revision Use reset-controller framework to assert/de-assert reset signals while configuring serdes lanes Corrected the logic for freeing NVMEM buffer Corrected the logic for waitng for assert/de-assert to happen Added configuring USB PIPE3 signals during reset release	http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
Zynq Devcfg	drivers/char/xilinx_devcfg.c	Revert "char: devcfg: Add bitstream version check	http://www.wiki.xilinx.com/Solution+Zynq+PL+Programming
ZynqMP Fpga Manager	drivers/fpga/zynqmp-fpga.c	Fix ZynqMP name in print. zynqmp: Add fpga image information struct.	http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming#x-Programming%20the%20PL%20through%20Linux
Zynq/ZynqMP GPIO	drivers/gpio/gpio-zynq.c	Wakeup gpio controller when it is used as IRQ controller	http://www.wiki.xilinx.com/Linux+GPIO+Driver
axi_gpio	drivers/gpio/gpio-xilinx.c	Add simple remove and exit functions There is missing clk handling and also dual mode. This fragment is taken from mainline gpio driver and it is required for module testing. xilinx: Fix the NULL pointer access. Prevent the NULL pointer access in the suspend resume.	http://www.wiki.xilinx.com/AXI+GPIO
ZynqMP pinctrl	drivers/pinctrl/pinctrl-zynqmp.c	Resolved pin conflicts 1bit and 4bit data lane support for sdio Updated pmu pin groups Warning on IO Standard mismatch Updated error handling in config set Added support for drive strength configuration zynqmp: Reset pin config when it's freed Fix code and documentation warnings	http://www.wiki.xilinx.com/ZynqMP+Linux+Pin+Controller+Driver
Zynq/ZynqMP I2C Controller	drivers/i2c/busses/i2c-cadence.c	Fix pin controller failure Fix the i2c Bus Recovery issue. cadence: Added slave support Fix wording in i2c-cadence driver	http://www.wiki.xilinx.com/Cadence+I2C+Driver
Zynq/ZynqMP Watchdog	drivers/watchdog/cadence_wdt.c	cadence_wdt: Fix the suspend resume. constify watchdog_ops structures.	http://www.wiki.xilinx.com/Cadence+WDT+Driver
Xilinx DRM KMS	drivers/gpu/drm/xilinx/*.c	Align with 4.7/4.8/4.9 kernel changes Fix the issue with DP 1.1 sink Handle the aux timeout	http://www.wiki.xilinx.com/Xilinx+DRM+KMS+driver

DTG Bug Fixes

Module Name	Bug Fixes	Link
Axi Ethernet	Change axi_ethernet compatible if it is 2.5g capable(xlnx,axi-2_5-gig-ethernet-1.0) and also don't generate xlnx,eth-hasnobuf property for 2.5g mac Enhance the logic to get the dma connected to axi_ethernet Add xlnx,include-dre property	http://www.wiki.xilinx.com/Build+Device+Tree+Blob
Uartps	Update uartps baudrate in chosen node, baud rate value should be configured value, if uartps is console device
Axi Dma	Change the axi dma compatible string to xlnx,eth-dma when DMA is connected to 10G/25G Soft IP MAC or 1G or 10G Add xlnx,include-dre property
Gem	Add is-internal-pcspma property to gem node, when ethernet is in SGMII mode and no external PCS/PMA found
Axi can	Update can_clk if device clock and axi clock are different, i.e generate two different clock names
Static dts files	Sync all relevant dts files with linux kernel

Answer Records (ARs)

Module Name	AR Title	AR Link
Zynq, ZynqMP Ethernet, macb	Zynq UltraScale+ MPSoC - SGMII using PS-GTR - Why is ZynqMP PHY driver reconfiguring the lanes previously set up for SGMII by the FSBL?	https://www.xilinx.com/support/answers/68866.html
Zynq, ZynqMP Ethernet, macb	MACB - MDIO support for single MAC managing multiple PHYs	https://www.xilinx.com/support/answers/69132.html
Zynq UltraScale+ MPSoC SATA	Zynq UltraScale+ MPSoC: PetaLinux Correct suspend/resume calls to work when FPD is off	https://www.xilinx.com/support/answers/69100.html

USB 2.0 OTG Driver

Xilinx Wiki

2017.1 Linux and DTG Release Notes

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