Zynq Base TRD 14.4

History
ISE DS 14.3 Targeted Base Reference Design
ISE DS 14.2 Targeted Base Reference Design
ISE DS 14.1 Targeted Base Reference Design

1 Introduction

This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 SoC device. For additional information, refer to Zynq-7000 SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide.

1.1 About the Base TRD

The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 SoC device for the embedded domain. The Base TRD consists of two elements: The Zynq-7000 SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 SoC based PS or as a hardware accelerator inside the SoC based PL. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. For additional information, please refer to UG925: Zynq-7000 SoC: ZC702 Base Targeted Reference Design User Guide.

1.2 Download the TRD

An archive with the TRD files can be downloaded here (requires to sign up).

1.3 Base TRD Package Contents

The Zynq Base TRD package is released with the source code, Xilinx PlanAhead and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.

2 Prerequisites

• The ZC702 Evaluation Kit ships with the Xilinx ISE Design Suite Embedded Edition version 14.x Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device and all required licenses to build the TRD. For additional information, refer to UG798 ISE Design Suite 14: Installation and Licensing Guide. A 30-day evaluation license can be generated after registering a Xilinx account.
• Xilinx IP evaluation licenses for the Video Timing Controller and Chroma Resampler IP cores can be ordered online.
• Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license. License options are listed on the Xylon logiCVC-ML product site.

Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-built bitfiles and boot images are built from a full logiCVC IP core and don't expire.

• A Linux development PC with the ARM GNU tools installed. The ARM GNU tools are included with the Xilinx ISE Design Suite Embedded Edition or can be downloaded separately.
• A Linux development PC with the distributed version control system Git installed. For more information, refer to the Xilinx Git wiki and to UG821: Xilinx Zynq-7000 SoC Software Developers Guide.

3 Building the FPGA Hardware Bitstream

This section explains how to generate the FPGA hardware bitsream using the Xilinx PlanAhead tool and how to export the hardware platform to Xilinx Software Development Kit (SDK) for software application development. Inside the PlanAhead project, a Xilinx Platform Studio (XPS) project is referenced that contains the actual hardware design.

3.1 Building the Bitstream

A pre-compiled bitstream can be found at $ZYNQ_TRD_HOME/boot_image/system.bit.

Steps for building the FPGA hardware bitstream

Launch PlanAhead:

• On Windows 7, select Start > All Programs > Xilinx Design Tools 14.x > ISE Design Suite 14.x > PlanAhead >PlanAhead.
• On Linux, enter planAhead at the command prompt.

From the PlanAhead welcome screen, click Open Project from the Getting Started group.


Open the PlanAhead project provided in the package. Click Browse and navigate to the $ZYNQ_TRD_HOME/hw/pa_proj project folder, select zynq_base_trd.ppr in the Open Project window, and press OK.



In the Flow Navigator pane on the left-hand side under Program and Debug, click Generate Bitstream. The bitstream will be generated at $ZYNQ_TRD_HOME/hw/pa_proj/zynq_base_trd.runs/impl_1/system_stub.bit.


Note: A message window will pop up, saying there are few critical warning messages. Ignore these warnings and press OK to continue with the bitstream generation.

3.2 Exporting the Hardware Platform to SDK

A pre-generated hardware platform project can be found at $ZYNQ_TRD_HOME/sw/hw_platform.
Steps for exporting the hardware platform to SDK
.
From the PlanAhead menu bar, select File > Export > Export Hardware

In the Export Hardware window press OK. The SDK hardware platform will be exported to $ZYNQ_TRD_HOME/hw/pa_proj/zynq_base_trd.sdk/SDK/SDK_Export.


Note: If the Launch SDK option is checked in the Export Hardware window, SDK will be launched immediately after SDK export has completed. This is not recommended at this point.

4 Building the First Stage Boot Loader (FSBL)

This section explains how to import and build the First Stage Boot Loader (FSBL) and the standalone OS based Board Support Package(BSP) from the provided SDK projects. A pre-compiled FSBL executable can be found at $ZYNQ_TRD_HOME/boot_image/zynq_fsbl.elf.

Note: The provided FSBL project is a customized version of the FSBL SDK project template. The following features have been added to the Base TRD version:

• added I2C initialization sequence for HDMI transmitter (ADV7511) on ZC702 base board
• added I2C FMC detection sequence
• added I2C initialization sequence for HDMI receiver (ADV7611) on Avnet IMAGEON FMC

Steps for building the FSBL

Launch Xilinx SDK:

• On Windows 7, select Start > All Programs > Xilinx Design Tools 14.x > ISE Design Suite 14.x > EDK > Xilinx Software Development Kit.
• On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/sw, then click OK. Close the welcome screen.


To import the hardware platform (hw_platform) and FSBL (zynq_fsbl) SDK projects into the SDK workspace, select File > Import.




Note: The zynq_fsbl project requires a hardware platform SDK project generated by SDK export. Instead of the provided hw_platform project, the one generated in Section 3.2 can be used. This requires the user to update the project reference of the zynq_fsbl project. This is not recommended at this point.

In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.




All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/sw. Press OK.


Make sure the hw_platform, standalone_bsp and zynq_fsbl projects are checked and uncheck the sobel_cmd and sobel_qt projects for now. Press Finish.





The build process will start automatically and builds the BSP first and then the FSBL. The generated Zynq FSBL executable can be found at $ZYNQ_TRD_HOME/sw/zynq_fsbl/Debug/zynq_fsbl.elf. This option can be changed by unchecking Project > Build Automatically from the menu bar.




To manually build the project, right click zynq_fsbl in the Project Explorer and select Build Project; to clean the project, select Clean Project.