NAND
NAND
Table of Contents
Introduction
This page gives an overview of Zynq Ultrascale+ MPSoC nand driver which is located at drivers/mtd/nand/arasan_nfc.c. link: nand source fileNAND driver provides basic functions that are required for accessing the nand flash memory including the support for hw ecc and bad block management.
HW IP Features
Controller Features
- Complies with the ONFI 3.1 specification
- Supports interleaving operations
- Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
- All ONFI 3.1 commands
- PIO and MDMA support
- SDR and NVDDR modes
- supports only 8-bit bus support
- Hardware ECC (Hamming code and BCH)
- Page size up to 16K
- Programmable timing modes
- 64-bit dma support.
- Supports multiple chip selects (up to 2)
Driver Features
- Supports only the mandatory ONFI 3.1 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
- Supports SDR/DDR modes
- Supports timing modes 0-5
- Supports PIO and MDMA support
- Support for multiple chip selection
- Support 64-bit dma
- Support BBT management
- Hardware ECC (Hamming code and BCH upto 24 bits)
Missing features, Known Issues, limitations
- No support for interleaved and all optional ONFI 3.1 commands
Bad Block management
Bad block management implementation is same as Linux MTD bad block management with the exception of reserving number of blocks to store Bad Block Table (BBT) from default 4 blocks to 64 blocks. This is because one of the Micron flash part MT29F32G08ABCDB has last 32 blocks as bad most of the times. Since it was difficult to store bad block table in last 4 blocks, the number of blocks are increased to 64 blocks.Kernel Configuration Options
The following config options should be enabled in order to build Zynq Ultrascale+ MPSoCCONFIG_MTD_NAND_ARASAN
CONFIG_MTD_NAND
Device Tree Settings
More information on nand device tree node details, refer the link nand device tree
Example for device tree
Nand Partition details
Below example assumes that controller is using 2 chip select lines
Testing procedure
Prerequisites
Kernel tools
mtd layer provides a rich set of tests for validating the nand access including the performance and stress testsFollowing kernel config options should be enabled for mtd tests
CONFIG_MTD_TESTS
user space tools
Below test cases requires the following user space toolsmtd_debug, nandtest
All these tools are part of the mtd-utils and source is available from link http://git.infradead.org/mtd-utils.git
Note: expected output may not be same and its all depends on the flash device and configuration of the target system.
Driver Probe
Assuming the target has nand flash memory installedHow to Run
Boot the target till Linux and ensure that nand driver is enabled.Expected Output
Block Erase test
How to Run
After linux boot,Expected Output
Write Page test
How to Run
After linux boot,Create a test image
Expected Output
Read Page and Data integrity test
How to Run
After linux boot,Expected Output
Data integrity test using nandtest utility
How to Run
After linux boot,Expected Output
MTD oob test
How to Run
After linux boot,Expected Output
MTD speed test
How to Run
After Linux boot,Expected Output
MTD stress test
How to Run
After Linux boot,Expected Output
MTD page read test
How to Run
After Linux boot,Expected Output
Note: Paths for the modules and tool names may vary from release to release. Please cross verify before starting the test.Change Log
2016.3
- Summary
- Added runtime clock gating support
- Fix the chip select/de select order to aid the runtime clock gating support
- Commits
- a6295324d67df0f6e2395e41133aafa551e0bb85 nand: arasan: Add runtime support
- 314921fb4618b9e73910c36a81067821ca3f6b6e nand: arasan: balance the select and deselect
- Summary
2016.4
- Summary
- None
- Commits
- None
- Summary
2017.1
2017.2
2017.3