Introduction

This page gives an overview of MIPI CSI-2 Transmit Subsystem driver which is available as part of the Xilinx Vivado and SDK distribution.

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/csi2txss


v_csi2txss
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-- doc - Provides the API and data structure details
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- examples - Reference application to show how to use the driver APIs and calling sequence
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- src - Driver source files

Core and Driver Features:

• Support for 1 to 4 D-PHY lanes
• Maximum data rate of 1.5 Gb/s
• Multiple data type support (RAW, RGB, YUV, User defined)
• Support for single, dual, quad pixel modes
• Support for 1 to 4 virtual channels
• Low power state (LPS) insertion between the packets
• Ultra low power (ULP) mode generation using register access
• Interrupt generation to indicate subsystem status information
• AXI4-Lite interface for register access to configure different subsystem options
• Configurable Line Start/Line End packet generation
• Configurable selection of D-PHY register interface

Test cases

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/csi2txss/examples