This wiki page complements the 2016.2 version of the Base TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Base TRD overview page.

1 Revision History

Change Log:

• Update all projects, IP and tools versions to 2016.2
• Add PMU firmware

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2 Overview

The Zynq UltraScale+ MPSoC Base Targeted Reference Design (TRD) is an embedded video processing application running on a combination of APU (SMP Linux), RPU (bare-metal) and PL.

The design consists of the following video data paths:

• Two video capture pipelines:
  • one capturing video from a test pattern generator (TPG) implemented inside the PL
  • the other capturing video from an external HDMI source via FMC daughter card (optional)
• A memory-to-memory processing pipeline implementing a 2D-convolution filter with programmable coefficients.
• A display pipeline with two layers, one used for video and the other for a graphical user interface (GUI) rendered by the GPU.

The TRD demonstrates the value of offloading computation intensive tasks like the 2D-convolution filter from the PS onto PL, thereby freeing APU resources. The APU load is plotted on the GUI to compare a pure software vs hardware accelerated implementation. The RPU is used to monitor the live memory throughput of the design by reading the built-in AXI performance monitors (APM) inside the PS. The data is sent to the APU via the OpenAMP communication framework and plotted on the GUI.

This wiki contains information about:

• How to setup the ZCU102 evaluation board and run the reference design.
• How to build all the TRD components based on the provided source files via detailed step-by-step tutorials.

Additional material that is not hosted on the wiki:

• User Guide containing information about system, software and hardware architecture.
• Reference Design Zip File including all source code and project files.
• Third Party Library Sources for separately licensed material that is not included in the reference design.

Note: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.

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3 Software Tools and System Requirements

3.1 Hardware

Required:

• ZCU102 evaluation board (rev B or newer) / power cable
• Monitor with DisplayPort input supporting one of the following resolutions:
  • 3840x2160 or
  • 1920x1080 or
  • 1280x720
• Display Port cable (DP certified)
• USB hub with mouse and keyboard
• SD card

Optional:

• Avnet FMC-HDMI-CAM daughter card / HDMI cable
• HDMI video source with input resolution set to:
  • 1080p60 for 1080p60 display or
  • 720p60 for 720p60 display

3.2 Software Tools

Required:

• Linux host machine for all tool flow tutorials (see here for detailed OS requirements)
• SDSoC Development Environment version 2016.2
• Xilinx Software Development Kit (XSDK) version 2016.2
• PetaLinux Tools version 2016.2
• Git distributed version control system
• GNU make utility version 3.81 or higher

Optional:

• Silicon Labs quad CP210x USB-to-UART bridge driver
• Serial terminal emulator e.g. teraterm

3.3 Licensing

The video Test Pattern Generator IP inside the Vivado project requires a license which can be obtained from here.

Steps to generate the license:

1. Click on the link mentioned above.
2. Fill in the login details and proceed.
3. Click on “Generate Node-Locked License" icon as shown in the picture:
   
4. Under system information, give the host details.
5. Proceed until you get the license agreement and accept it.
6. The License (.lic file) will be sent to the email-id mentioned in the login details.
7. Copy the license file locally and give the same path in the SDSOC license manager.

3.4 Compatibility

The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:

DisplayPort Cable:

• Cable Matters DisplayPort Cable-E342987
• Monster Advanced DisplayPort Cable-E194698

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4 Design File Hierarchy

The Zynq UltraScale+ MPSoC Base TRD zip file is released with the source code including PetaLinux BSP, SDSoC and Xilinx SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 evaluation board. The top-level directory structure is shown in the figure below.

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5 Installation and Operating Instructions

5.1 Board Setup

Required:

• Connect power supply to J52.
• Connect USB mouse and keyboard using a USB hub to J83.
• Connect DisplayPort cable to P11; connect other end to monitor.
• Insert SD card (FAT formatted) with binaries copied from TRD_HOME/sdcard directory.
• Select one of the provided autostart shell scripts based on your desired display resolution and rename it:
  • for 3840x2160 (4K), rename the file autostart_2160p.sh to autostart.sh
  • for 1920x1080, rename the file autostart_1080p.sh to autostart.sh
  • for 1280x720, rename the file autostart_720p.sh to autostart.sh

Optional:

• Connect FMC-HDMI-CAM to HPC0 FMC slot.
• Connect HDMI cable to HDMI IN port of FMC-HDMI-CAM; connect other end to HDMI source.
• Vadj needs to be set to 1.8V (default) for correct operation.
• Connect micro-USB cable to J83 USB UART connector; use the following settings for your terminal emulator:
  • Baud Rate: 115200
  • Data: 8 bit
  • Parity: None
  • Stop: 1 bit
  • Flow Control: None

Jumpers & Switches:

• Set boot mode switch to SD boot (SW6[4:1] - on,off,on,off).
• Configure USB 2.0 jumpers for host mode (default - see ZCU102 eval board user guide).