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MIPI DSI-2 TX Subsystem Standalone Driver

MIPI DSI-2 TX Subsystem Standalone Driver

Introduction

The Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Transmitter Subsystem implements a DSI transmit interface in adherence to the MIPI DSI standard v2.0 (Type 4 architecture). The subsystem receives a pixel stream from an AXI4-Stream interface and inserts the required markers, such as hsync start and hsync end, in accordance with the DSI protocol and user-programmed options. The packet frame is sent over a MIPI D-PHY or C-PHY transmitter based on the number of lanes selected. The PHY interface is compliant with MIPI D-PHY Specification v2.0 and MIPI C-PHY Specification v2.0. The subsystem allows fast selection of the top-level parameters and automates most of the lower-level parameterization. The AXI4-Stream interface allows a seamless interface to other AXI4-Stream-based subsystems.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

Driver Name

Path in Vitis

Path in Github

dsitxss

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dsitxss

embeddedsw/XilinxProcessorIPLib/drivers/dsitxss at master · Xilinx/embeddedsw · GitHub

 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2025.2 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/dsitxss at xlnx_rel_v2025.2 · Xilinx/embeddedsw · GitHub

 

The driver source code is organized into different folders. The table below shows the dsitxss driver source organization.

Directory

Description

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl, .yaml and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree-based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow. The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver API Documentation

The complete API reference and data structure documentation for the MIPI DSI-2 TX Subsystem standalone driver is available at dsitxss: Main Page. This documentation provides details on driver functions, configuration structures, interrupt handling, and example usage generated from the driver source documentation.

Driver Implementation

For a full list of features supported by this IP, please refer to the MIPI DSI-2 Transmitter Subsystem Product Guide (PG238).  

Features

The MIPI DSI-2 Transmitter Subsystem Standalone driver supports the following features:

  • Support for one to four D-PHY lanes and one to three C-PHY lanes.

  • Internal MIPI D-PHY/C-PHY support enables direct connection to a MIPI DSI-compliant display panel, based on the selected PHY mode and lane configuration.

  • Line rates ranging from 260 to 2500 Mb/s for AMD Versal™ adaptive SoCs; 80 to 2500 Mb/s for other supported device families, subject to the device datasheet; and 400 to 2500 Mb/s for D-PHY mode / 400 to 1000 Msym/s for C-PHY mode on Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2 devices.

  • Supports different data types with a fixed Virtual Channel Identifier (VC) of 0: RGB888, RGB565, RGB666 loosely packed, RGB666 packed, and Compressed.

  • Support for 1, 2, and 4 pixels per clock at the input as defined in AXI4-Stream Video IP and System Design Guide (UG934).

  • Programmable EoTp generation support.

  • ECC generation for packet header.

  • CRC generation for data bytes (optional).

  • Optional DCS (Display Command Set) command mode support for sending short and long command packets to the display panel for initialization, configuration, and control.

  • Pixel-to-byte conversion based on data format.

  • AXI4-Lite interface to access core registers.

  • Compliant with AXI4-Stream Video IP and System Design Guide (UG934) for input video stream.

  • Interrupt generation to indicate subsystem status information.

Known Issues and Limitations

The following is a list of known limitations of the driver and features of the IP that are not currently implemented: 

  • DCS commands that require bi-directional MIPI I/O, including Bus Turn Around (BTA), are not supported.

  • Optional DSI sub-link features are not supported.

  • Non-continuous clock mode is not supported.

  • Dynamic line rate change is not supported.

  • LPDT and ULPS escape mode support is not available in the standalone driver.

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

MIPI DSI TX Subsystem does not support the application example design generation. For MIPI DSI TX example design, refer to MIPI CSI-2 RX Subsystem Application example design, which uses MIPI DSI TX Subsystem for display option. This example design also allows you to test the MIPI DSI only path using the Test Pattern Generator.

For more information, see MIPI CSI-2 Receiver Subsystem Product Guide (PG232).

Examples Path:
embeddedsw/XilinxProcessorIPLib/drivers/mipicsiss/examples at master · Xilinx/embeddedsw

Test/Application Name

Example Source

Description

Test/Application Name

Example Source

Description

Self Test

xdsitxss_selftest_example.c

This example does a basic reset of the core and checks core is coming out of reset or not.

xmipi_example

xmipi_example.c

This example application is built to demonstrate the functionality of the MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the Zynq ultrascale+ based ZCU102 platform.

xmipi_sp701_example

xmipi_sp701_example.c

This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD Spartan™ 7 FPGA platform.

xmipi_vck190_example

xmipi_vck190_example.c

This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD the versal based VCK190 platform.

xmipi_vek280_example

xmipi_vek280_example.c

This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD the versal based VEK280 platform.

Example Application Usage

The Application Example Design demonstrates the use of the MIPI CSI-2 RX Subsystem and MIPI DSI TX Subsystem on an AMD Zynq™ UltraScale+™ ZCU102 board. On the capture path, the system receives images captured by an IMX274 image sensor. Processed images are displayed on either the HDMI monitor or the MIPI DSI display.

A block diagram of the MIPI CSI-2 RX Subsystem and MIPI DSI-2 TX subsystem application example design is shown in the following figure.

MIPI-CSI2-RX-Subsystem-Application-Example-Design-Block-Diagram.png

 

The MIPI CSI-2 RX Subsystem decodes, processes video data and presents on AXI4-Stream data with two pixels data per clock. The RAW video data is then converted into RGB data using the Demosaic IP, V_Gamma_Lut, V_Proc_SS CSC IPs, two pixels at a time.

RGB data is then fed to the Video Test Pattern Generator IP (V-TPG). The TPG is available in the design to act as an alternate source of video in case no MIPI CSI-2 video source is present. The TPG (in pass-through mode) sends video packets across the AXI4-Stream data in dual pixel per beat mode to an AXI4-Stream broadcaster.

The broadcaster is used to broadcast the stream to the MIPI DSI TX Subsystem or HDMI TX Subsystem to be displayed. The HDMI TX Subsystem is available as an alternative if a MIPI DSI-compliant display panel is not available. Using the GPIO IP, one of the destination video paths is selected. The GPIO enables the TREADY signal in the selected path. If the MIPI DSI TX Subsystem path is chosen, the video is passed through a video processing subsystem configured as a Scaler. This is required as the MIPI DSI Panel works on a fixed resolution of 1920x1200. All videos must either be up scaled (480p, 720p, 1080p) or downscaled (4K) to 1920x1200 resolution for the MIPI DSI display panel.

Expected Output

-------------------------------------------------- ------ MIPI Reference Pipeline Design ---------- --------- (c) 2017 by Xilinx, Inc. ------------- -------------------------------------------------- -------------------------------------------------- Build May 5 2025 - 09:18:45 -------------------------------------------------- Please answer the following questions about the hardware setup. Is the camera sensor connected? (Y/N) y Camera sensor is set as Connected Is the DSI Display panel connected? (Y/N) y DSI Display panel is set as Connected InitVprocSs_Scaler Done InitDSI Done -------------------------------- Color Depth = RAW10 Setting Color Depth = 10 bpc --------------------------------- Disable CAM_RST of Sensor through GPIO Sensor is Enabled ******************************************** Test Input Stream: 3840x2160@60Hz (RGB8) ******************************************** Stride is calculated 11520 Frame Buffer Setup is Done HDMI is disconnected. Enabling DSI Tready ... Enabled --------------------- --- MAIN MENU --- --------------------- s - Select Video Source : Sensor. t - Select Video Source : TPG. h - Select Display Device : HDMI d - Select Display Device : DSI r - Change the video resolution 720p/1080p/4K. -------------Current Pipe Configuration------------- Color Depth : RAW10 Source : Sensor Destination : DSI Resolution : 3840x2160@60 Lanes : 4 Lanes ----------------------------------------------------- Set TPG as source -------------Current Pipe Configuration------------- Color Depth : RAW10 Source : Test Pattern Generator Destination : DSI Resolution : 3840x2160@60 Lanes : 4 Lanes ----------------------------------------------------- --------------------------- --- RESOLUTION MENU --- --------------------------- 1 - 1280 x 720p@60fps 2 - 1920 x 1080p@30fps 3 - 1920 x 1080p@60fps 4 - 3840 x 2160p@30fps 5 - 3840 x 2160p@60fps 99 - Exit Enter Selection -> 1 ******************************************** Test Input Stream: 1280x720@60Hz (RGB8) ******************************************** Stride is calculated 3840 Frame Buffer Setup is Done -------------Current Pipe Configuration------------- Color Depth : RAW10 Source : Test Pattern Generator Destination : DSI Resolution : 1280x720@60 Lanes : 4 Lanes -----------------------------------------------------

 

Sequence Diagram

The sequence diagram illustrates the usage of the MIPI CSI‑2 RX Subsystem and the MIPI DSI TX Subsystem. It is based on the example application and the MIPI DSI TX Subsystem driver on the AMD Versal™ VCK190 platform. Please refer to the attached sequence diagram PDF for the full initialization and data-flow sequence: .

Example Design Architecture

The MIPI DSI-2 TX Subsystem standalone example usage is demonstrated as part of the shared MIPI CSI-2 RX and MIPI DSI TX reference pipeline. The reference design receives video from the MIPI CSI-2 RX path or the Video Test Pattern Generator (TPG), processes/scales the stream as required, and displays the output through the MIPI DSI TX Subsystem or HDMI TX Subsystem.

The example pipeline is:

IMX274 Sensor / TPG -> MIPI CSI-2 RX Subsystem -> Video Processing -> AXI4-Stream Broadcaster -> MIPI DSI TX / HDMI TX

The MIPI DSI-2 TX Subsystem contains the following major sub-cores:

Sub-Core

Function

Sub-Core

Function

MIPI D-PHY / C-PHY

Physical layer interface that transmits serial MIPI data to the display panel.

DSI TX Controller

Protocol layer that frames DSI packets, handles the fixed virtual channel, inserts sync markers such as hsync start and hsync end, and manages EoTp, ECC, and CRC generation based on subsystem configuration.

Pixel-to-Byte Converter

Converts incoming AXI4-Stream pixel data to byte-oriented DSI packet payloads based on the configured data format and pixels-per-clock setting.

Refer to the block diagram in the Example Application Usage section and the MIPI DSI-2 Transmitter Subsystem Product Guide (PG238) for additional architecture and configuration details.

Performance

For detailed performance specifications of the MIPI DSI-2 TX Subsystem, including supported resolutions, frame rates, throughput, lane configuration, line rate, PHY mode, pixels per clock, and resource utilization, refer to the MIPI DSI-2 Transmitter Subsystem Product Guide (PG238). Performance depends on the selected device family, subsystem configuration, number of lanes, PHY mode, pixels per clock, line rate, data type, display timing, and overall system design.

Change Log

2026.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2026.1 · Xilinx/embeddedsw

2025.2

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.2 · Xilinx/embeddedsw

2025.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.1 · Xilinx/embeddedsw

Related Links

This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI-2) TX subsystem soft IP.