MIPI DSI-2 TX Subsystem Standalone Driver
Introduction
The Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Transmitter Subsystem implements a DSI transmit interface in adherence to the MIPI DSI standard v2.0 (Type 4 architecture). The subsystem receives a pixel stream from an AXI4-Stream interface and inserts the required markers (such as hsync start, hsync end) in accordance with the DSI protocol and user-programmed options. The packet framed is sent over a MIPI D-PHY or C-PHY (Compliant with MIPI Alliance Standard for D-PHY/C-PHY Specification, version 2.0) transmitter based on the number of lanes selected. The subsystem allows fast selection of the top-level parameters and automates most of the lower-level parameterization. The AXI4-Stream interface allows a seamless interface to other AXI4-Stream-based subsystems.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
dsitxss | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dsitxss | embeddedsw/XilinxProcessorIPLib/drivers/dsitxss at master · Xilinx/embeddedsw · GitHub |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2025.2 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/dsitxss at xlnx_rel_v2025.2 · Xilinx/embeddedsw · GitHub
The driver source code is organized into different folders. The table below shows the mipicsiss driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .yaml and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree-based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow. The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
Driver Implementation
For a full list of features supported by this IP, please refer to the MIPI DSI-2 Transmitter Subsystem Product Guide (PG238).
Features
The MIPI CSI-2 Receiver Subsystem Standalone driver supports the following features:
1-4 Lanes D-PHY and 1-3 Lanes C-PHY Support
Line rates ranging from:
260 to 2500 Mb/s for AMD Versal™ adaptive SoCs
80 to 2500 Mb/s, refer to the datasheet of your device
400 to 2500 Mb/s for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2:
400 to 2500 Mb/s for D-PHY mode
400 to 1000 Ms/s for C-PHY mode
Supports different data types with a fixed Virtual Channel Identifier (VC) of 0. For a list of data types, refer to the DSI Data type GUI parameter
Programmable EoTp generation support
ECC generation for packet header
CRC generation for data bytes (optional)
Optional DCS Command mode support to send command packets long/short
Optional LPDT and ULPS Escape mode support
Pixel-to-byte conversion based on data format
AXI4-Lite interface to access core registers
Compliant with AXI4-Stream Video IP and System Design Guide (UG934) for input video stream
Interrupt generation to indicate subsystem status information
Known Issues and Limitations
The following is a list of known limitations of the driver and features of the IP that are not currently implemented:
None
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
MIPI DSI TX Subsystem does not support the application example design generation. For MIPI DSI TX example design, refer to MIPI CSI-2 RX Subsystem Application example design, which uses MIPI DSI TX Subsystem for display option. This example design also allows you to test the MIPI DSI only path using the Test Pattern Generator.
For more information, see MIPI CSI-2 Receiver Subsystem Product Guide (PG232).
Examples Path:
embeddedsw/XilinxProcessorIPLib/drivers/mipicsiss/examples at master · Xilinx/embeddedsw
Test/Application Name | Example Source | Description |
|---|---|---|
Self Test | This example does a basic reset of the core and checks core is coming out of reset or not. | |
xmipi_example | This example application is built to demonstrate the functionality of the MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the Zynq ultrascale+ based ZCU102 platform. | |
xmipi_sp701_example | This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD Spartan™ 7 FPGA platform. | |
xmipi_vck190_example | This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD the versal based VCK190 platform. | |
xmipi_vek280_example | This example application is built to demonstrate the functionality of MIPI CSI-2 RX and MIPI DSI-2 TX subsystem running on the AMD the versal based VEK280 platform. |
Example Application Usage
The Application Example Design demonstrates the use of the MIPI CSI-2 RX Subsystem and MIPI DSI TX Subsystem on an AMD Zynq™ UltraScale+™ ZCU102 board. On the capture path, the system receives images captured by an IMX274 image sensor. Processed images are displayed on either the HDMI monitor or the MIPI DSI display.
A block diagram of the MIPI CSI-2 RX Subsystem and MIPI DSI-2 TX subsystem application example design is shown in the following figure.
The MIPI CSI-2 RX Subsystem decodes, processes video data and presents on AXI4-Stream data with two pixels data per clock. The RAW video data is then converted into RGB data using the Demosaic IP, V_Gamma_Lut, V_Proc_SS CSC IPs, two pixels at a time.
RGB data is then fed to the Video Test Pattern Generator IP (V-TPG). The TPG is available in the design to act as an alternate source of video in case no MIPI CSI-2 video source is present. The TPG (in pass-through mode) sends video packets across the AXI4-Stream data in dual pixel per beat mode to an AXI4-Stream broadcaster.
The broadcaster is used to broadcast the stream to the MIPI DSI TX Subsystem or HDMI TX Subsystem to be displayed. The HDMI TX Subsystem is available as an alternative if a MIPI DSI-compliant display panel is not available. Using the GPIO IP, one of the destination video paths is selected. The GPIO enables the TREADY signal in the selected path. If the MIPI DSI TX Subsystem path is chosen, the video is passed through a video processing subsystem configured as a Scaler. This is required as the MIPI DSI Panel works on a fixed resolution of 1920x1200. All videos must either be up scaled (480p, 720p, 1080p) or downscaled (4K) to 1920x1200 resolution for the MIPI DSI display panel.
Expected Output
--------------------------------------------------
------ MIPI Reference Pipeline Design ----------
--------- (c) 2017 by Xilinx, Inc. -------------
--------------------------------------------------
--------------------------------------------------
Build May 5 2025 - 09:18:45
--------------------------------------------------
Please answer the following questions about the hardware setup.
Is the camera sensor connected? (Y/N)
y
Camera sensor is set as Connected
Is the DSI Display panel connected? (Y/N)
y
DSI Display panel is set as Connected
InitVprocSs_Scaler Done
InitDSI Done
--------------------------------
Color Depth = RAW10
Setting Color Depth = 10 bpc
---------------------------------
Disable CAM_RST of Sensor through GPIO
Sensor is Enabled
********************************************
Test Input Stream: 3840x2160@60Hz (RGB8)
********************************************
Stride is calculated 11520
Frame Buffer Setup is Done
HDMI is disconnected.
Enabling DSI Tready ... Enabled
---------------------
--- MAIN MENU ---
---------------------
s - Select Video Source : Sensor.
t - Select Video Source : TPG.
h - Select Display Device : HDMI
d - Select Display Device : DSI
r - Change the video resolution 720p/1080p/4K.
-------------Current Pipe Configuration-------------
Color Depth : RAW10
Source : Sensor
Destination : DSI
Resolution : 3840x2160@60
Lanes : 4 Lanes
-----------------------------------------------------
Set TPG as source
-------------Current Pipe Configuration-------------
Color Depth : RAW10
Source : Test Pattern Generator
Destination : DSI
Resolution : 3840x2160@60
Lanes : 4 Lanes
-----------------------------------------------------
---------------------------
--- RESOLUTION MENU ---
---------------------------
1 - 1280 x 720p@60fps
2 - 1920 x 1080p@30fps
3 - 1920 x 1080p@60fps
4 - 3840 x 2160p@30fps
5 - 3840 x 2160p@60fps
99 - Exit
Enter Selection -> 1
********************************************
Test Input Stream: 1280x720@60Hz (RGB8)
********************************************
Stride is calculated 3840
Frame Buffer Setup is Done
-------------Current Pipe Configuration-------------
Color Depth : RAW10
Source : Test Pattern Generator
Destination : DSI
Resolution : 1280x720@60
Lanes : 4 Lanes
-----------------------------------------------------
Sequence Diagram
The sequence diagram illustrates the usage of the MIPI CSI‑2 RX Subsystem and the MIPI DSI TX Subsystem. It is based on the example application and the MIPI DSI TX Subsystem driver on the AMD Versal™ VCK190 platform. Please refer to the
Example Design Architecture
NA
Performance
NA
Change Log
2025.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2025.2/doc/ChangeLog#L528
2025.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2025.1/doc/ChangeLog#L2885
Related Links
This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI-2) TX subsystem soft IP.