Zynq UltraScale MPSoC Base TRD 2016.3 - Design Module 6
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This module shows how to add a Test Pattern Generator (TPG) implemented in the PL.
This module requires the following components:
- zcu102_base_trd (Vivado)
- device tree (system-dm6.dts)
Build Flow Tutorials
PL Base TRD
This tutorial shows how to build the Base TRD Vivado design that implements the TPG capture pipeline.
Create a Vivado project. Select 'es1' instead if you are targeting a rev D board with ES1 silicon.
- Implement the design and generate a bitstream
Copy the generated bitstream to the PetaLinux directory or alternatively use the pre-built bit file that is already bundled with the PetaLinux BSP.
Please refer to design module 1 - PMU firmware
for instructions or skip this step if you have built the PMU firmware in a previous module.
This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
The petalinux-config step can be skipped if this was already done in a previous module.
Select the device-tree matching design module 6 and build all Linux image components. If you have run petalinux-build in a previous module, the build step will be incremental.
Create a boot image.
Copy the generated boot image and Linux image to the dm6 SD card directory.
Copy the file autostart.sh from the pre-built dm9 SD card directory.
Video Qt Application
There is no need to rebuild the video_qt2 application if you have already built it in module 5, otherwise follow the instructions from module 5.
Run Flow Tutorial