Linux EDAC Driver

Created by Confluence Wiki Admin (Unlicensed)
Last updated Feb 22, 2021 by lakshmis

Table of Contents


Overview

This documents provides driver details about the Synopsys DDR ECC controller driver used in Zynq and ZynqMP SOC.

HW/IP Features

Zynq DDRC controller and ZynqMP SOC DDRC Controller supports single bit error correction and double bit error detection
ZynqMP DDRC controller has interrupt support and error injection support.
Zynq DDRC controller reports the single and double bit errors based on poll method.
ZynqMP DDRC controller reports the single and double bit errors based on interrupt method.

Missing features, Known Issues and Limitations

  • None

Kernel Configurations


The following kernel configuration options should be enabled for compiling the Synopsys EDAC driver
CONFIG_EDAC_SYNOPSYS = y

Device tree Node Settings

Refer the device tree bindings doc.
Documentation/devicetree/bindings/memory-controllers/synopsys.txt

For ZynqMP SOC device tree bindings doc
refer devicetree bindings doc

For Zynq SOC
For ZynqMP SOC


Mainline Status

This driver is in mainline.

Fixes related to coverity warning are not yet in mainline (~3 lines).

Test Procedure

Zynq

To test the EDAC driver on Zynq platform manually, below are the changes required in FSBL and U-Boot source:

FSBL changes:

U-boot Changes:


Use the above changes in FSBL and U-Boot and compile Images.

Use the compiled FSBL and U-Boot Images while booting linux.

Now after booting Linux:


ZynqMP




Expected Output

Zynq

ZynqMP

Change log

2016.3

  • Summary
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  • Commits
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2016.4

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2017.1

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2017.2

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2017.3

  • Summary
    • Do not use symbolic permissions
  • Commits

2017.4

  • Summary
    • Fix for incorrect Macro defines
  • Commits

2018.1

  • Summary
    • Add Memory mapping, 16bit row mode and video buffer mode support
  • Commits

2018.2

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    • None
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2018.3

2019.1

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2019.2

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    • None
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2020.1

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    • None
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    • None

2020.2

  • Summary
    • Fix the wrong value assignment for edac_mode.
  • Commits

Related Links