/*This page contains info for Frame buffer Read IP too as there is a single driver for both Frame buffer Read and Write IP.

Table of Contents

The purpose of this page is to describe the the Xilinx Framebuffer Write / Read DMA driver. Video Framebuffer Write / Read IP cores are designed for video applications requiring frame buffers and is designed for high-bandwidth access between the AXI4-Stream video interface and the AXI4-interface.This supports reading and writing a variety of video formats (RGB, YUV 4:4:4, YUV 4:2:2, YUV 4:2:0, Luma only and RGB/BGR/YUV with alpha (only for Read)). The data is packed/unpacked based on the video format. Planar and semi-planar memory formats are available for YUV 4:2:2 and YUV 4:2:0. The memory video format, stride, and frame buffer address are run time programmable. The driver is present in the Xilinx Linux-xlnx github at -  https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_frmbuf.c

Interfacing with the Video Framebuffer Driver from DMA Clients

The Linux driver for Framebuffer Write implements the Linux DMA Engine interface semantics for a single channel DMA controller. Because the IP is video format aware, it has capabilities that are not fully served by the dma engine interface. As such, the Video Framebuffer driver exports an API interface that must be used by DMA clients in addition to the Linux DMA Engine interface for proper programming. (see xilinx_frmbuf.h).

The general steps for preparing DMA to write to a specific memory buffer:

1. Using the Video Framebuffer API, configure the DMA device with the expected memory format for write

2. Prepare an interleaved template describing the buffer location (note: see section DMA Interleaved Template Requirements below for more details)

3. Pass the interleaved template to the DMA device using the Linux DMA Engine interface

4. With the DMA descriptor which is returned from step 3, add a callback and then submit to the DMA device via the DMA Engine interface

5. Start the DMA write operation

6. Terminate DMA write operation when frame processing deemed complete by client
   
   
   

DMA Interleaved Template Requirements

The Video Framebuffer IP supports two dma address pointers for semi-planar formats: one for luma and one for chroma. As such, data for the two planes need not be strictly contiguous which permits for alignment of plane data within a larger buffer. However, all frame data (luma and chroma) must be contained within a single, larger contiguous frame buffer and luma plane data should be arranged to come before chroma data within this frame buffer space. Note that this is not a limitation imposed by the IP but by the driver at this moment. When preparing a struct dma_interleaved_template instance to describe a semi-planar format, the following members must be filled out as follows:

From linux/dmaengine.h:

struct dma_interleaved_template:

dst_start = <physical address from which to start reading frame data (any offsets should be added to this value)>
src_sgl = false
dst_sgl = true
numf = <height of frame in pixels; height of luma frame for semi-planar formats>
frame_size = < 1 or 2 depending on whether this is describing a packed or semi-planar format>
sgl = <see struct data_chunk below>

struct data_chunk:

sgl[0].size = <number of bytes devoted to image data for a row>
sgl[0].icg = < number of non-data bytes within a row of image data; padding>
sgl[0].dst_sgl = <the offset in bytes between the end of luma frame data to the start of chroma plane data; only needed for semi-planar formats>

Below is a code example for semi-planar YUV 422 (i.e. NV16) demonstrating how steps 1 and 2 of the above code snippet change in such a case:

Driver Operation

The Framebuffer driver manages buffer descriptors in software keeping them in one of four possible states in the following order:

1. pending

2. staged

3. active

4. done

When a DMA client calls dma_commit(), the buffer descriptor is placed in the driver’s “pending” queue. Multiple buffers can be queued in this manner by the DMA client before proceeding to the next step (see step 4 of Interfacing with the Video Framebuffer Driver from DMA Clients).

When dma_async_issue_pending() is called (step 5 in the client code sample above), the driver begins processing all queued buffers on the “pending” list. A buffer is picked from the pending list and then stored as “staged”. At this moment, driver programs the registers with data provided within the “staged” buffer descriptor. During normal processing (i.e. all frames except the first frame*), these values will not become active until the currently processed frame completes. As such, there is a one-frame delay between programming and the actual writing data to memory. Hence the term “staged” to describe this part of the buffer lifecycle.

When the currently active frame completed, the buffer descriptor is classified as “active” in the driver. At this point, a new descriptor is picked from the pending list and this new buffer is marked as “staged” with its values programmed into the IP registers as described earlier. The buffer marked “active” represents the data currently being written to memory. Other than being held in the “active” state, no other action is taken with the buffer

When the active frame completes, it is moved to the “done” list. The driver utilizes a tasklet which is called at the end of the frame interrupt handler. The tasklet will process any buffer descriptors on the done list by removing them from the list and calling any callback the client has linked to the descriptor.

This completes the life cycle of a buffer descriptor. As can be seen, with four possible states, it is best to allocate at least four buffers to maintain consistent frame processing. Fewer buffers will result in gaps within the pipeline and result in frame data within a given buffer being overwritten one or more times (depending on how few buffers are queued and the number of resulting gaps in the driver’s buffer pipeline).

Buffer Alignment

The driver expects the buffer to be aligned to at least 8 * <pixels per clock> bytes. For e.g. if pixels per clock is 2 then the buffer has to be at least 16 byte aligned.

In case some other system component, like VCU, mandates the buffer should be aligned to higher value, e.g. 32 byte aligned, the user is expected to set this manually in the device tree using xlnx,dma-align dt property.

Refer to the device tree bindings doc for details.

• Note: normally, registers programmed while the IP is running will not take effect until the next frame. The very first frame, however, is an exception: the IP is not yet running and, as such, the values take effect immediately. Nevertheless, there is no additional special treatment given the first frame buffer. As such, it will be written to, in effect, twice.

IP/Driver Features

Missing Features / Known Issues / Limitations in Driver

• Tested for standard resolutions up to 8K

• YUV 12 and 16 BPC color formats support added in IP in 2019.1 but are not supported in driver in 2019.1.
  
  

• The first buffer returned by the driver will contain the second frame contents, after this the driver will correctly give the data

• When DMA operations are initiated by a client, the hardware is placed into "autorestart" mode. When the last buffer has been returned to the client as "completed", if the client does not supply a new write/read buffer location or fails to halt the driver, then the last buffer location written to will continue to be utilized by the driver. In effect, the driver will "spin" on the last location programmed.

• For 2020.2, the field id reported in the IP register may be incorrect due to bug in IP / Vitis HLS tool.

Kernel Configuration

The driver must be enabled in the kernel by selecting option CONFIG_XILINX_FRMBUF

Device Tree Binding

Complete documentation on the device tree requirements may be found in the Linux source located at xilinx_frmbuf.yaml

Testing Procedure

To ensure the Framebuffer Write IP Linux driver has been configured to work properly, a suitable test design will require an input source (i.e. HDMI Rx) connected to the Framebuffer.
Once properly configured, the design can be tested via the tool known as "yavta". yavta may be found here.

To run yavta, data must be streaming into your media pipeline. To verify the status of your media pipleline, run the tool known as "media-ctl":

In the above example, entity 5 represents the HDMI Rx input source which happens to be receiving YUYV-based media at 1080p resolution. The Video Framebuffer driver is managed/controlled by a V4L2 "client" driver represented by entity 1. The above pipeline is suitable for capturing and writing to memory any of the supported YUV 8-bit formats (e.g. YUYV, NV16 or NV16M).

A frame capture to local binary files can now be performed using the yavta tool:

The above command syntax specifies 10 frames to capture (-c10) writing to memory in packed YUYV format (-f YUYV) with 1920x1080 dimensions (-s 1920x1080) and to only write out the last 3 frames captured to a file (--skip 7). These instructions are sent to the file descriptor which represents the V4L2 driver controlling, ulimately, the Video Framebuffer (-F /dev/video0).

Lastly, we list the contents of the directory within which we execute the yavta command and we see three files named frame-* . These files can be opened in a viewer utility like yuvplayer.exe an inspected to ensure that frame capture occurred properly.

The Frame Buffer Read IP Linux driver has been tested with the Xilinx DRM framework PL display driver, Video mixer and with encoder drivers such as SDI Tx, HDMI Tx, DP Tx and MIPI DSI Tx. This has been done using modetest, X11 (ran xclock with twm) and gstreamer kmssink plugins. Testing the Framebuffer Read driver is best done when incorporated into a larger design designed for display output. It is best to reference the test procedure for the Video Mixer. In particular, run test #6 (change output resolution).
Additionally, run modetest to change the output resolution with the -v argument which will result in page flipping on the primary plane

The output frequency reported should be approximately 1/4 that of the current refresh rate. This is because modetest only creates a single framebuffer and the Video Framebuffer driver requires four (4) buffers for optimal operation.

Boards Supported

• ZCU102

• ZCU106

• VCK190/VMK180

• VEK280

• VEK385

Known Issues

• AR68765 - LogiCORE Video Frame Buffer Write - Release Notes and Known Issues for the Vivado 2017.1 tool and later versions

Change Log

2025.1

• Summary

  • Add YUV444 12bit 3planar format

  • New driver for Video Framebuffer IP

• Commits

  • 3049fa7 dmaengine: xilinx_frmbuf: Add YUV444 12bit format

  • 0776e03 dmaengine: xilinx_frmbuf: New driver for Video Framebuffer IP

2024.2

• Summary

  • No changes

2024.1

• Summary

  • No changes

2023.1

• Summary

  • No changes

2022.2

• Summary

  • Add support for 3 planar YUV 444 10 bits per component

2022.1

• Summary

  • No changes

2021.2

• Summary

  • Add support for 3 planar YUV 444 8 bits per component

  • Add support for 15360 x 8640 resolution

  • Fix code alignment

  • Update the SPDX license header

  • Fix kernel doc warning

  • Add support for field id error detection

  • Correct the ADDR3 register offset

• Commits

  • dmaengine: xilinx: frmbuf: Add support for 3 planar YUV444 8bpc

  • dmaengine: xilinx: frmbuf: Add support for max 15360x8640 resolution

  • dmaengine: xilinx: frmbuf: Fix code alignment to match paranthesis

  • dmaengine: xilinx: frmbuf: Update to SPDX license header

  • dmaengine: xilinx: frmbuf: Fix kernel doc warning

  • dmaengine: xilinx: frmbuf: Add support for field id error detection

  • engine: xilinx: frmbuf: Correct ADDR3 register offset to support 3 pl…

2021.1

• Summary

  • Export pixels per clock as width alignment for dma clients

• Commits

  • dmaengine: xilinx: frmbuf: Export width alignment

2020.2

• Summary

  • Correctly free up resources while removing dma

  • Fix Y10 v4l2 pixel format

  • Fix for Coverity warnins

  • Use AP_DONE instead of AP_READY

• Commits

  • dmaengine: xilinx: frmbuf: Replace AP_READY with AP_DONE

  • dmaengine: xilinx: frmbuf: Fix warnings for UNINIT

  • dmaengine: xilinx: frmbuf: Fix warnings for PW.MIXED_ENUM_TYPE

  • dmaengine: xilinx: frmbuf: Fix Y10 v4l2 pixel format

  • dmaengine: xilinx: frmbuf: add missing controller free when removing …

2020.1

• Summary

  • Add support 8 ppc

• Commits

  • bb91ad8 dmaengine: xilinx: frmbuf: Add support for 8 ppc

2019.2

• Summary

  • Add support for low latency capture

• Commits

  • 107831e v4l: xilinx: dma: Use early callback mode for low latency capture

  • 9308da3 Revert "Revert "dma: xilinx: Release buffers before DMA transfer""

  • 4036801 Revert "dma: xilinx: Release buffers before DMA transfer"

2019.1

• Summary

  • Make max-width, max-height dt properties mandatory

  • Support 12,16 bpc RGB color formats

  • Support early callback using bitmask

  • Call the call back registered just before programming the descriptor in EARLY_CALLBACK_LOW_LATENCY mode.

  • Add clock framework support

• Commits

  • 09e6f94 dmaengine: xilinx: frmbuf: Make max-width and max-height mandatory properties

  • 04fc254 dmaengine: xilinx: frmbuf: Add support for 12 and 16 bpc RGB formats

  • 6ce7c27 dma: xilinx: Release buffers before DMA transfer

  • d0489cb dma: xilinx: Support early callback modes

  • 1d2bb41 dma: xilinx: Add clock framework support to Framebuffer driver

2018.3

• Summary

  • Add default mode for non streaming use case which has only states.

  • Add early callback support

  • Mark previous active descriptor as complete in irq handler

  • Add check for max-width and height

• Commits

  • 2b189f4 dma: xilinx: Add early callback support to Framebuffer Driver

  • 96b495c dma: xilinx: Add API to set framebuffer IP mode

  • a7b77ed dma: xilinx: Mark previous active decriptor as complete in irq handler

  • d75dca59 dma: xilinx: Add check for max width and height in Framebuffer Read/Write

2018.2

• Summary

  • Flush FIFO on halt.

  • Get DMA alignment from pixels per clock or dma-align device tree properties

  • Add interlaced support

• Commits

  • ecc3314 dma: xilinx: Add fid property for interlaced support in framebuffer

  • 699b419 dma: xilinx: Flush the framebuffer FIFO on halt

  • f805b07 dma: xilinx: Get DMA alignment from device tree for Framebuffer

  • 16c2f51 dma: xilinx: Add alpha formats support for Framebuffer Read

  • 705bac9 dma: xilinx: Add interlaced support to Xilinx Framebuffer driver

2018.1

• Summary

  • Add XV15, XV20, BGR8, RGBA8, YUVA8, RGBX10, YUVX10, Y_UV10, Y_UV10_420, Y10, BGRA8, BGRX8 and UYVY8 color formats

  • Fix V4L2 PIX FORMAT for BGRX8

• Commits

  • 9fc4f30 dma: Add support for XV15 and XV20 contiguous formats

  • d5e10bf dma: xilinx: Correct the V4L fourcc for BGRX8 in framebuffer driver

  • 59643ff dma: xilinx: Add support for BGR8 color format in Framebuffer

  • d6fe7f5 dma: xilinx: Update Framebuffer Driver with support for new 8-bit/10-bit formats

2017.4

• Summary

  • No changes

2017.3

• Summary

  • Add initial driver version

• Commits

  • f618d3b dma: xilinx: Add private API to permit retrieval of supported mem formats

  • 7858ca5 dma: xilinx: Bug fix to ensure GPIO is reset between DMA operations

  • e506e84 Bug fix to ensure only video formats enabled in IP are in driver

  • 49026f2 dma: xilinx: Update to Framebuffer Driver to support dual addr pointers

  • 166f3ac dma: xilinx: New driver for Video Framebuffer IP

Related Links

• Video Frame Buffer Read/Write Product Guide

• Linux Drivers