This wiki page complements the 2016.3 version of the Base TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Base TRD overview page.

Change Log:

• Update all projects, IP and tools versions to 2016.3

• Add support for ZCU102 rev 1.0 board with ES2 silicon

• Split reference design into 9 design modules with dedicated tutorials

• Remove support for HDMI input via FMC-HDMI-CAM

• Add USB webcam support for video capture (USB2 only!)

• Add virtual video device (vivid) support for video capture

• Use X11 Qt and Mali backend instead of fbdev

The Zynq UltraScale+ MPSoC Base Targeted Reference Design (TRD) is an embedded video processing application running on a combination of APU (SMP Linux), RPU (bare-metal) and PL.

The design consists of the following video data paths:

• Video capture pipelines capturing video from:

  • a virtual video device (vivid) implemented purely in software

  • a USB webcam connected to the PS (optional)

  • a test pattern generator (TPG) implemented inside the PL

• A memory-to-memory processing pipeline implementing a 2D-convolution filter with programmable coefficients.

• A display pipeline with two layers, one used for video and the other for a graphical user interface (GUI) rendered by the GPU.

The TRD demonstrates the value of offloading computation intensive tasks like the 2D-convolution filter from the PS onto PL, thereby freeing APU resources. The APU load is plotted on the GUI to compare a pure software vs hardware accelerated implementation. The RPU is used to monitor the live memory throughput of the design by reading the built-in AXI performance monitors (APM) inside the PS. The data is sent to the APU via the OpenAMP communication framework and plotted on the GUI.

This wiki contains information about:

• How to setup the ZCU102 evaluation board and run the reference design.

• How to build all the TRD components based on the provided source files via detailed step-by-step tutorials.

Additional material that is not hosted on the wiki:

• User Guide containing information about system, software and hardware architecture.

• Reference Design Zip File for ZCU102 rev 1.0 / ES2 silicon including all source code and project files.

• Reference Design Zip File for ZCU102 rev D / ES1 silicon including all source code and project files.

• Third Party Library Sources for separately licensed material that is not included in the reference design.

Note: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.

Required:

• ZCU102 evaluation board / power cable

• Monitor with DisplayPort input supporting one of the following resolutions:

  • 3840x2160 or

  • 1920x1080 or

  • 1280x720

• Display Port cable (DP certified)

• USB hub with mouse and keyboard

• SD card

Optional:

• USB webcam

Required:

• Linux host machine for all tool flow tutorials (see here for detailed OS requirements)

• SDSoC Development Environment version 2016.3

• Xilinx Software Development Kit (XSDK) version 2016.3

• PetaLinux Tools version 2016.3

• Git distributed version control system

• GNU make utility version 3.81 or higher

Optional:

• Silicon Labs quad CP210x USB-to-UART bridge driver

• Serial terminal emulator e.g. teraterm

The video Test Pattern Generator IP inside the Vivado project requires a license which can be obtained from here.

Steps to generate the license:

1. Click on the link mentioned above.

2. Fill in the login details and proceed.

3. Click on “Generate Node-Locked License" icon as shown in the picture:
   
   

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4. Under system information, give the host details.

5. Proceed until you get the license agreement and accept it.

6. The License (.lic file) will be sent to the email-id mentioned in the login details.

7. Copy the license file locally and give the same path in the SDSOC license manager.

The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:

DisplayPort Cable:

• Cable Matters DisplayPort Cable-E342987

• Monster Advanced DisplayPort Cable-E194698

USB Webcam:

The top-level directory structure is shown in the figure below.

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The reference design is split into 9 design modules DM1 to DM9:

• DM1 – APU SMP Linux

• DM2 – RPU0 FreeRTOS Application

• DM3 – RPU1 Bare-metal Application

• DM4 – APU/RPU1 Inter Process Communication

• DM5 – APU Qt Application

• DM6 – PL Video Capture

• DM7 – OpenCV-based Image Processing

• DM8 – PL-accelerated Image Processing

• DM9 – Full-fledged Base TRD

Each module is described in more detail in UG1221 and on the respective tutorial page.

The following table shows the dependency matrix between different modules. For example: DM6 (row) depends on or builds on top of modules DM1 and DM5 (columns).

The below figure shows the relevant design components for DM9 as well as inter-dependencies and generated output products.

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The below table shows which design components are used in which design modules. A graphical view for each design module is provided on the respective design module tutorial page.