Zynq UltraScale MPSoC Base TRD 2016.4 - Design Module 3
Return to the Design Tutorials Overview.
This module demonstrates:
- Boot RPU1 only
- Bare-metal performance monitor application
- Reads PS APM counters to measure CCI, Core Switch and DDR throughput and latency, then prints them to UART1
This module requires the following components:
- perfapm-ctl + perfapm
Build Flow Tutorials
Please refer to design module 1 - PMU firmware
for instructions or skip this step if you have built the PMU firmware in a previous module.
This tutorial shows how to build the first stage bootloader (FSBL) and boot image using the PetaLinux build tool.
The petalinux-config step can be skipped if this was already done in a previous module.
Build the FSBL. This step can be skipped if this was already done in a previous module.
Create a boot image
Copy the generated boot image to the dm3 SD card directory
Run Flow Tutorial
- See here for board setup instructions.
- Copy all the files from the $TRD_HOME/images/dm3 SD card directory to a FAT formatted SD card.
- Power on the board to boot the images; make sure all power rail LEDs are lit green.
- The user can now see FSBL and PMU-firmware prints on UART-0 and prints from baremetal Perfapm-ctl application can be viewed on UART-1.
- When prompted, user need to press 'Y' to turn on a dummy traffic generator that reads from OCM
- View the application prints on UART-1 as shown in the pictures: