Data Movers

This page contains all Data Movers resources for Zynq-7000 SoC.

Resources

User Guides

App Notes & Reference Designs & White Papers

• Overview of Zynq-7000 SoC data mover examples

• Functional description of the ZC702 base targeted reference design, including IP/logic implemented in programmable logic (PL) and base TRD package directory structure.

• Summarizes the PCIe TRD modes of operation and features including PCIe connectivity and Cortex A9 processing and offload.

• App Note describes how a Xilinx XADC can be used for system monitoring applications.

• App Note describes how the Xilinx XADC acquires analog data using its dedicated Vp/Vn analog input.

• App Note describes how to use Vivado HLS to develop a floating-point matrix multiplication accelerator with an AXI4-Stream interface and connect it to the ACP of the ARM CPU.

• App Note demonstrates Vivado subsystem for endpoint-initiated DMA data transfers through PCI Express.

• App Note describes the tool flow, concepts and techniques for using partial reconfiguration on Zynq-SoC through the DevC and PCAP.

• App Note describes using the PS based gigabit Ethernet MAC (GEM) through the EMIO interface with the 1000BASE-X physical interface using high speed serial transceivers in the PL.

• This example design allocates 4K of block RAM attached to the CPU via M_AXI_GP0

Tech Tips & How To's

• Zynq-7000 SoC Getting Started
• Zynq-7000 SoC Demonstrations & Boards and Kits
• Zynq-7000 SoC Development & Debug
• Zynq-7000 SoC Boot & Config
• Zynq-7000 SoC Operating Systems
• Zynq-7000 SoC Power Management
• Zynq-7000 SoC Performance and Benchmarks
• Zynq-7000 SoC Software Acceleration
• Zynq-7000 SoC Real-Time & Data Movement
• Zynq-7000 SoC Peripherals, IP & Drivers
• Zynq-7000 SoC Security & Safety