Zynq Base TRD 2013.3

Table of Contents

1 Introduction

1.1 About the Base TRD

1.2 Download the TRD

1.3 Base TRD Package Contents

2 Prerequisites

3 Building the FPGA Hardware Bitstream

3.1 Building the Bitstream

3.2 Steps for exporting the hardware platform to SDK

4 Building the First Stage Boot Loader (FSBL)

5 Installation of Petalinux SDK

5.1 Prerequisites

5.2 Extract the PetaLinux Package

5.3 Install License

5.4 Setup PetaLinux Working Environment

5.4 Verify Petalinux Installation

6 Zynq Base TRD BSP Installation

7 Add Linux kernel 3.10 support

8 Build Petalinux.

9 Generate BOOT image for Zynq

10 Running Video Demo Applications

10.1 Hardware Setup Requirements

10.2 Board Setup

10.3 Run Qt GUI Application in 1080p mode.

10.4 Run Qt GUI Application in 720p mode.

10.5 Run UART Menu Application in 1080p mode.

10.6 Run UART Menu Application in 720p mode

11 References

12 Appendix

12.1 Vivado HLS Flow for generating Sobel filter Vivado IP

12.2 EDID Extended display identification data .

12.3 Add Custom resolution to sobel application

12.4 Known Issues

History
Vivado 2013.2 Targeted Base Reference Design
ISE DS 14.5 Targeted Base Reference Design
ISE DS 14.4 Targeted Base Reference Design
ISE DS 14.3 Targeted Base Reference Design
ISE DS 14.2 Targeted Base Reference Design
ISE DS 14.1 Targeted Base Reference Design

1 Introduction

This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 All Programmable SoC (AP SoC) device. For additional information, refer to Zynq-7000 All Programmable SoC: ZC702 Evaluation Kit and Video and Imaging Kit Getting Started Guide.

1.1 About the Base TRD

The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 AP SoC device for the embedded domain. The Base TRD consists of two elements: The Zynq-7000 AP SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The AP SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 AP SoC based PS or as a hardware accelerator inside the AP SoC based PL. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. For additional information, please refer to UG925: Zynq-7000 All Programmable SoC: ZC702 Base Targeted Reference Design User Guide.

1.2 Download the TRD

An archive with the TRD files can be downloaded here .

1.3 Base TRD Package Contents

The Zynq Base TRD package is released with the source code, Xilinx Vivado and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 AP SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.

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2 Prerequisites

• The ZC702 Evaluation Kit ships with the Xilinx Vivado™ Design Suite Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device and all required licenses to build the TRD. For additional information, refer to UG798 ISE Design Suite 14: Installation and Licensing Guide. A 30-day evaluation license can be generated after registering a Xilinx account.

• Xilinx IP evaluation licenses for the Video Timing Controller and Chroma Resampler IP cores can be ordered online.

• Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license. License options are listed on the Xylon logiCVC-ML product site.

Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-built bitfile and boot images are built from a full logiCVC IP core and don't expire.

• A Linux development PC with the ARM GNU tools installed.

• A Linux development PC with the distributed version control system Git installed. For more information, refer to the Xilinx Git wiki and to UG821: Xilinx Zynq-7000 AP SoC Software Developers Guide.

• A Linux development PC with Petalinux SDK installed . For more information , refer to Xilinx Petalinux user manuals .

• A Linux development PC with QT and QWT libraries cross-compiled for Zynq platform. Set ZYNQ_QT_INSTALL environment variable by referring to Xilinx Zynq Qt/Qwt Libraries - Build Instructions

3 Building the FPGA Hardware Bitstream

This section explains how to generate the FPGA hardware bitstream using the Xilinx Vivado tool and how to export the hardware platform to Xilinx Software Development Kit (SDK) for software application development.

3.1 Building the Bitstream

Steps for building the FPGA hardware bitstream

Launch Vivado :

• On Windows 7, select Start > All Programs > Xilinx Design Tools > Vivado 2013.3 > Vivado 2013.3.

• On Linux, enter vivado at the command prompt.

NOTE for Windows users: Copy directory 'vivado' that is at '$ZYNQ_TRD_HOME/hardware/' to a drive directly because of windows file path limit (255 characters) before following the next steps for building hardware bitstream.

From the Vivado welcome screen, in TCL console, run following commands
1. cd $ZYNQ_TRD_HOME/hardware/vivado
2. source ./scripts/project.tcl

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The above step creates a project 'zynq_base_trd_2013.3'.

In the Flow Navigator pane on the left-hand side under Program and Debug, click Generate Bitstream. The bitstream will be generated at $ZYNQ_TRD_HOME/hardware/vivado/project/zynq_base_trd_2013.3.runs/impl_1/system_top_wrapper.bit

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Exporting the Hardware Platform to SDK
A pre-generated hardware platform project can be found at $ZYNQ_TRD_HOME/software/workspace/hw_platform/.

3.2 Steps for exporting the hardware platform to SDK

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From the Vivado menu bar, select File > Export > Export Hardware for SDK

In the Export Hardware window press OK. The SDK hardware platform will be exported to $ZYNQ_TRD_HOME/hardware/vivado/project/zynq_base_trd_2013.3.sdk/SDK/SDK_Export.

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Note: If the Launch SDK option is checked in the Export Hardware window, SDK will be launched immediately after SDK export has completed. This is not recommended at this point.

4 Building the First Stage Boot Loader (FSBL)

This section explains how to import and build the First Stage Boot Loader (FSBL) and the standalone OS based Board Support Package(BSP) from the provided SDK projects.

Note: The provided FSBL project is a customized version of the FSBL SDK project template. The following features have been added to the Base TRD version:

• I2C mux reset.

• FMC detection sequence.

• I2C initialization sequence for HDMI receiver (ADV7611) on Avnet IMAGEON FMC.

All the above customizations are added to FsblHookBeforeHandoff routine part of
$ZYNQ_TRD_HOME/software/workspace/zynq_fsbl/src/fsbl_hooks.c.

Steps for building the FSBL
Launch Xilinx SDK:

• On Windows 7, select Start > All Programs > Xilinx Design Tools > SDK 2013.3 > Xilinx SDK 2013.3.

• On Linux, enter xsdk at the command prompt.

In the Workspace Launcher window, click Browse and navigate to $ZYNQ_TRD_HOME/software/workspace, then click OK. Close the welcome screen.

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To import the hardware platform (hw_platform) , FSBL (zynq_fsbl) and FSBL BSP (zynq_fsbl_bsp) into the SDK workspace,
Select File > Import.

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Note: The zynq_fsbl project requires a hardware platform SDK project generated by SDK export. Instead of the provided hw_platform project, the one generated in Section 3.2 can be used.
This requires the user to update the project reference of the zynq_fsbl project.
In the Import wizard, expand the General folder, select Existing Projects into Workspace, and click Next.

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All projects are located at the top-level inside your SDK workspace. Click Browse and navigate to $ZYNQ_TRD_HOME/software/workspace. Press OK.

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Make sure the hw_platform, zynq_fsbl and zynq_fsbl_bsp projects are checked . Press Finish.

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The build process will start automatically and builds the BSP first and then the FSBL. The generated Zynq FSBL executable can be found at $ZYNQ_TRD_HOME/software/workspace/zynq_fsbl/Debug/zynq_fsbl.elf. This option can be changed by unchecking Project > Build Automatically from the menu bar.

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To manually build the project, right click zynq_fsbl in the Project Explorer and select Build Project; To clean the project, select Clean Project.

5 Installation of Petalinux SDK

5.1 Prerequisites

• 2GB RAM (recommended minimum for Xilinx tools)

• Pentium 4 2GHz CPU clock or equivalent.

• 5 GB free HDD space.

• Supported OS:

  • RHEL 5 (32-bit or 64-bit)

  • RHEL 6 (32-bit or 64-bit)

  • SUSE Enterprise 11 (32-bit or 64-bit)

• PetaLinux release package downloaded.

• Valid PetaLinux license.

• Common system packages and libraries are installed on your workstation. The installation process will check for these. See the section Required Tools and Libraries for more details. For detailed information refer petalinux installation guide UG976 .

Download Petalinux 2013.10 SDK software from Xilinx website download section.

5.2 Extract the PetaLinux Package

Assuming all the prerequisites described in the last subsection are satisfied, PetaLinux installation is very straight forward.Without any options, the installer will installl as a subdirectory of the current directory. Alternatively, an installation path may be specific . Run the downloaded petalinux installer.

PetaLinux will be installed in the petalinux-v2013.10-final directory, directly underneath the working directory of this command.
So, if you install the installer into your home directory /home/user, PetaLinux will be installed in /home/user/petalinux-v2013.10-final.
You may move the resulting petalinux-v2013.10-final directory to a preferred location before continuing.

5.3 Install License

PetaLinux licenses are managed using the same system as all other Xilinx Design Tools. For more details on licensing and setup of license please refer to the
"Xilinx Design Tools: Installation and Licensing Guide (UG798)" section "Obtaining and Managing a License".

5.4 Setup PetaLinux Working Environment

After extracting the package, the remainder of the setup is completed automatically.
1. Go to the PetaLinux root directory by running this command on the command console:
cd <path-to-installed-PetaLinux>
e.g.:

2. Source the appropriate PetaLinux setup script by running this command on the command console:
For Bash:

The first time the setup script is sourced, it will perform some post installation tasks to check system dependencies and initialise the Linux kernel source tree.
Below is an example of the output from sourcing the setup script for the first time:

PetaLinux environment set to ’/home/user/petalinux-v2013.10-final
INFO: Finalising PetaLinux installation
INFO: Checking free disk space
INFO: Checking installed tools
INFO: Checking installed development libraries
INFO: Checking network and other services
The post-install step only occurs once. Subsequent runs of the settings script should be much quicker, and simply output a confirmation message such as that shown below:
PetaLinux environment set to ’/home/user/petalinux-v2013.10-final'

5.4 Verify Petalinux Installation

Verify that the PetaLinux working environment has been set:

/home/user/petalinux-v2013.10-final
Environment variable "$PETALINUX" should point to the path to the installed PetaLinux. Your echo output may be different from this example, depending upon where you installed PetaLinux.

6 Zynq Base TRD BSP Installation

PetaLinux includes reference designs for you to start working with and customise for your own projects. These are provided in the form of installable BSP (Board Support Package) files, and include
all necessary design and configuration files, including pre-built and tested hardware and software images, ready for download to your board or for booting in the QEMU system simulation environment.
Run petalinux-create command on the command console:
petalinux-create -t project -s <path-to-bsp>

Example:

INFO: Create project:
INFO: Projects:
INFO: * zynq_base_trd_2013.3
<snip>

7 Add Linux kernel 3.10 support

Zynq Base TRD uses Xilinx Linux 3.10 kernel version.Petalinux provides option to add individual project specific kernel/u-boot version. Below steps demonstrates how to add/config/build the Linux kernel.

Create a new branch named zynq_base_trd_v2013.3 based on the xilinx-v14.7 tag.

Apply the Base TRD specific patch on top of the xilinx-v14.7. The patch includes:

• Mouse sensitivity patch (As default mouse sensitivity on embedded QT GUI is quite fast)

Petalinux configuration help us to select custom kernel required for Zynq Base TRD project.

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Select kernel menu in Linux configuration. It opens Kernel selection sub-menu.

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Select linux-xlnx kernel , exit and select yes for "Do you wish to save your new configuration ?" .
It updates kernel selection for petalinux build process.
NOTE : linux-xlnx sources points to 3.10 kernel version

8 Build Petalinux.

Finally, it’s time to build your petalinux image.TRD installable BSP auto-configures required software settings.

Run ’petalinux-build’ in the petalinux SDK project directory to build the PetaLinux system image:

Note: For more verbose build message use petalinux-build -v.

The console shows the compilation progress. e.g.:
INFO: Checking component...
INFO: Generating make files and build Linux
INFO: Generating make files for the subcomponents of linux
INFO: Building Linux
<snip>

And the compilation log are stored in build.log in the $(PETALINUX)/build directory.

9 Generate BOOT image for Zynq

Follow the steps below to generate the SD boot image (BOOT.BIN).

petalinux-package --boot --fsbl <Path to FSBL image> --fpga <Path to FPGA bitstream> --uboot=<Path to uboot image> -o <output file>

Required option for boot image package:
--fsbl <FSBL_ELF> Path to FSBL ELF image location
Options for boot image package:
--force Force overwrite the boot binary image
--fpga <BITSTREAM> Path to FPGA bitstream image location
--uboot[=<UBOOT_IMG>] Path to the u-boot elf image location
(default <PROJECT>/images/linux/u-boot.elf)

Prerequisite
petalinux-package command requires bootgen utility to be present in $PATH. Refer Vivado tools installation section for further information.

NOTE : In case only software component update is required ,user may prefer to use prebuilt FSBL and bistream binaries.
Bitstream : $PETALINUX/zynq_base_trd_2013.3/pre-built/linux/implementation/system_top_wrapper.bit
FSBL : $PETALINUX/zynq_base_trd_2013.3/pre-built/linux/images/zynq_fsbl.elf

Move to petalinux images directory.

SD BOOT mode Petalinux Deployment Binaries:
a) BOOT.BIN
b) image.ub
c) autostart.sh [$(ZYNQ_TRD_HOME)/ready_to_test]
Zynq Base TRD uses autostart.sh to invoke sobel QT application on start-up.
Uncomment below snippet to disable auto-start.
#run_sobel.sh -qt &

10 Running Video Demo Applications

This section explains through step by step instructions how to bring up the ZC702 board for video demonstration part of the TRD and running different video demonstrations out of the box.
The ZC702 Evaluation Kit comes with an SD-MMC card pre-loaded with binaries that enable the user to run the video demonstration and software applications. It also includes the binaries necessary to
configure and boot the Zynq-7000 AP SoC based ZC-702 board.

Note:
a) If the evaluation kit design files were downloaded online, copy the entire folder ZYNQ_TRD_HOME/ready_to_test from the package onto the primary partition of the SD-MMC card
which is formatted as FAT32 using a SD-MMC card reader.
b) Petalinux console login details:-
User : root
Password : root

10.1 Hardware Setup Requirements

The ZC702 board setup to run & test the video demonstration applications require the following items:

Requirements for TRD Linux application demo setup

• The ZC702 evaluation board with the XC7Z020 CLG484-1 part

• AC power adapter (12 VDC)

• Optional: An USB Type-A to USB Mini-B cable (for UART communications) and a Tera Term Pro (or similar) UART terminal program.

• USB-UART drivers from Silicon Labs

• A HDMI cable.

• Optional: FMC (FPGA Mezzanine Card).

• Optional: External Video Source e.g. Roku HD Streaming player.

• A SD-MMC flash card containing TRD binaries formatted with FAT32. The SD-MMC is pre-loaded with required binaries in its first partition. The pre-loaded binaries include :

  • BOOT.bin

  • image.ub

• An USB Micro-B to female Adaptor with USB hub is needed for connecting a keyboard and a mouse.

• An USB mouse and keyboard.

• A display monitor that supports HD resolutions: 1920 x 1080p @ 60 Hz, and 1280 x 720 @ 60 Hz(if the user also want to validate TRD with 720p video output)

Note:
It is recommended to use ZC702 production board.
TRD binaries has been tested with a Asus VS228 display monitor. However, the examples should work well with any HDMI-compatible output device provided it supports 720/1080p resolution in EDID information.

10.2 Board Setup

This section explains how to setup the ZC702 board to run and test video demonstration applications.
Steps for setting the board

Connect the cables as shown in Figure below to prepare the ZC702 board to run the TRD video demo applications.

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• Optional: Connect the HDMI FMC card (BD-FMC-IMAGEON-G). You can run this demo with out the external Video source. If you connect with out the external Video source, the demo will default to an internally generated video text pattern.

• Connect a display monitor to the HDMI out port of the ZC702 board using a HDMI cable.

• Connect a keyboard and mouse to an USB hub, which is connected to the ZC702 board Micro-B USB connector. (Keyboard is optional if just using the mouse in the Qt GUI)

• Optional: Connect an USB Mini-B cable into the Mini USB port J17 labeled USB UART on the ZC702 board and the USB Type-A cable end into an open USB port on the host PC for UART communications.

• Connect the power supply to the ZC702 board. Do not switch the power on.

• Insert a SD-MMC memory card, which contains the TRD binaries, into the SD slot on the ZC702 board.