Zynq Base TRD 2015.2

History
Vivado 2014.4 Targeted Base Reference Design
Vivado 2014.2 Targeted Base Reference Design
Vivado 2013.4 Targeted Base Reference Design
Vivado 2013.3 Targeted Base Reference Design
Vivado 2013.2 Targeted Base Reference Design
ISE DS 14.5 Targeted Base Reference Design
ISE DS 14.4 Targeted Base Reference Design
ISE DS 14.3 Targeted Base Reference Design
ISE DS 14.2 Targeted Base Reference Design
ISE DS 14.1 Targeted Base Reference Design

1 Introduction

This page provides instructions on how to build various components of the Zynq Base Targeted Reference Design (TRD) and how to setup the hardware platform and run the design on the ZC702 Evaluation Kit. The ZC702 Evaluation kit is based on a XC7Z020 1CLG484 Zynq-7000 SoC device.

1.1 About the Base TRD

The Base TRD is an embedded video processing application designed to showcase various features and capabilities of the Zynq Z-7020 SoC device for the embedded domain. The Base TRD consists of two elements: The Zynq-7000 SoC Processing System (PS) and a video processing pipeline implemented in Programmable Logic (PL). The SoC allows the user to implement a video processing algorithm that performs edge detection on an image (Sobel filter) either as a software program running on the Zynq-7000 SoC based PS or as a hardware accelerator inside the SoC based PL. The Base TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications. For additional , please refer to UG925: Zynq-7000 SoC: ZC702 Base Targeted Reference Design User Guide.

1.2 Download the TRD

An archive with the TRD files can be downloaded here .

1.3 Base TRD Package Contents

The Zynq Base TRD package is released with the source code, Xilinx Vivado and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.



1.4 Prerequisites

• The ZC702 Evaluation Kit ships with the Xilinx Vivado™ Design Suite Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device and all required licenses to build the TRD. For additional information, refer to Vivado Design Suite User Guide. A 30-day evaluation license can be generated after registering a Xilinx account.
• Xilinx IP evaluation licenses for the Video Timing Controller core can be ordered online.
• Xilinx PetaLinux tools version 2015.2
• Xylon logiCVC-ML is shipped as evaluation IP core that does not require a license. License options are listed on the Xylon logiCVC-ML product site.

Note: The provided logiCVC evaluation IP core has a 1 hour timeout built-in such that the display freezes after the timer expires. The pre-built bitfile and boot images are built from a full logiCVC IP core and don't expire.

• A Linux development PC with the ARM GNU tools installed.
• A Linux development PC with the distributed version control system Git installed. For information, refer to the Xilinx Git wiki and to UG821: Xilinx Zynq-7000 SoC Software Developers Guide.
• A Linux development PC with QT and QWT libraries cross-compiled for Zynq platform. Set ZYNQ_QT_INSTALL environment variable by referring to Xilinx Zynq Qt/Qwt Libraries - Build Instructions
• GNU make utility version 3.81 or higher.

1.5 Known Issues

• Test Pattern Generator (TPG) version 5 is used instead of version 6 (latest) to avoid TPG going out of frame boundary when video source is changed. In TPG selection, when the bouncing box touches the boundary of the monitor a horizontal line appears on the monitor.
• HDMI input is not working. The PG signal does not assert by default on early ZC702 boards. To be FMC compliant, the PG signal must be asserted when power rails are good. See AR51438 for solution.

2 Run the TRD demo

This section provides step by step instructions on how to bring up the ZC702 board for video demonstration part of the TRD and running different video demonstrations
out of the box.
The ZC702 Evaluation Kit comes with an SD-MMC card pre-loaded with binaries that enable the user to run the video demonstration and software applications.
It also includes the binaries necessary to configure and boot the Zynq-7000 SoC based ZC702 board.

Note:
a) If the evaluation kit design files were downloaded online, copy the entire folder content from $ZYNQ_TRD_HOME/ready_to_test onto the primary partition of the SD-MMC card which is formatted as FAT32 using a SD-MMC card reader.
b) Petalinux console login details:-
User : root
Password : root
c) In case user has optional FPGA Mezzanine Card (FMC) setup
ready_to_test/devicetree-fmc.dtb is renamed to devicetree.dtb and copy it to primary partition of SD-MMC card along with

• BOOT.BIN
• autostart.sh
• devicetree.dtb
• uImage
• uramdisk.image.gz
• bin/ __
  • |- run_video.sh
  • |- video_cmd
  • |- video_qt

2.1 Hardware Setup Requirements

Requirements for TRD Linux application demo setup

• The ZC702 evaluation board with the XC7Z020 CLG484-1 part
• AC power adapter (12 VDC)
• Optional: An USB Type-A to USB Mini-B cable (for UART communications) and a Tera Term Pro (or similar) UART terminal program.
• USB-UART drivers from Silicon Labs
• A HDMI cable.
• Optional: FMC (FPGA Mezzanine Card).
• Optional: External Video Source e.g. Roku HD Streaming player.
• A SD-MMC flash card containing TRD binaries formatted with FAT32. The SD-MMC is pre-loaded with required binaries in its first partition. The pre-loaded binaries include :
  • BOOT.BIN
  • uImage
  • devicetree.dtb
  • devicetree-fmc.dtb
  • uramdisk.image.gz
  • autostart.sh
  • bin/ __
    • |- run_video.sh
    • |- video_cmd
    • |- video_qt
• An USB Micro-B to female Adaptor with USB hub is needed for connecting a keyboard and a mouse.
• An