In this article we will demonstrate how to merge two BRAM controllers in Vivado IPI, and SDK.
The caveat to this flow is that the Vivado tools will treat each BRAM controller as a seperate memory. Therefor the MMI file will have two regions, and if the ELF
is too big, it will give an error. Also, in SDK to default linker script built by the tool will have two memory regions This article will show how to over come this.
Note: This flow will only support BRAM controllers that have the same address range, as the updatemem does not support mismatched bus blocks
Build the HW
In this demo, Vivado 2017.2 was used to create the Block Design. The two bram controller where added with a contigious address range:
The address map is shown below:
Note: This is just for demo purposes, the user could of course use 16KB in one bram controller.
Modifying the MMI:
As mentioned in the introduction, the two BRAM ranges will be treated as two independent memories. This will result in the MMI having two
separate memories. These can be merged together. This can be done to the MMI file in the SDK HW Platform in Project Explorer.
Select Open With Text Editor:
User will need to know the cell properties of the BRAM. To get this, open the implemented design, and do a Ctrl + f and PRIMITIVE_TYPE select BMEM.BRAM.
The placement (LOC) info from the cell properties is needed here. So, in the MMI we will add the second BUS_BLOCK:
For more information on the MMI syntax, see chapter 7 in the Embedded Processor Hardware Design Guide in related links.
Note:If user re-exports to SDK, then these changes will need to be made again.
Modifying the Linker script:
As mentioned in the introduction, the two BRAM ranges will be treated as two independent memories. This will result in the linker having two
separate memories. These can be merged together.
Right click on the application in Project Explorer in SDK, and open the linker in a text editor and make the changes similar to below:
Testing in Updatemem:
To test, I created an ELF that will cross my contiguous boundary:
Then use the Program FPGA from Xilinx Tools which will invoke updatemem:
- Embedded Processor Hardware Design : link