Table of Contents

1 Introduction

This tutorial shows how to develop a Partial Reconfiguration (PR) design for the Zynq-7000 SoC using the Xilinx Vivado Design Suite, Vivado HLS, Software Development Kit (XSDK), and PetaLinux design tools. It complements application note XAPP1231 which focuses on conceptual aspects of the PR flow and design considerations specific to the Zynq architecture.

The previous versions of this reference design is available at the links below: 

ISE 14.4 XAPP1159 - Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 SoC Devices

1.1 Design Overview

The PR reference design is built on top of the ZC702 Base Targeted Reference Design (TRD) , an embedded video processing application that demonstrates how it is best to separate control and data processing functions. In this example a compute-intensive video filtering algorithm is moved from the Processing System (PS) onto a hardware accelerator in Programmable Logic (PL). The image filter IP core demonstrated in the ZC702 Base TRD is a Sobel filter configured with edge detection coefficients which has been generated using Vivado HLS. For this reference design, three image filter IP cores are generated using Vivado HLS: Posterize, Sobel, FAST. The provided reference design demonstrates how to use software-controlled Partial Reconfiguration through the Processor Configuration Access Port (PCAP) to dynamically reconfigure part of the PL with the desired image filter IP core and observe the modified video output on a monitor.

1.2 Requirements

Software Tools

• Vivado Design Suite 2014.4 System Edition, includes Vivado High-Level Synthesis (HLS)

• Xilinx Software Development Kit 2014.4

• PetaLinux 2014.4

• Silicon Labs CP210x USB to UART Bridge VCP Driver

• Git distributed version control system (optional)

Note: Some tools are optional and the corresponding design flow tutorials can be skipped.

Hardware

• ZC702 Evaluation Kit

• Monitor with HDMI or DVI port that supports 1080p60 video resolution

• Avnet FMC-IMAGEON module and external video source that provides 1080p60 video input over HDMI (optional)

• USB mouse and keyboard (optional)

Licensing

• Xilinx Partial Reconfiguration is a product inside the Vivado Design Suite that requires a license

• Xilinx IP evaluation licenses may be provided with the Vivado Design Suite or can be ordered online

• Xylon logiCVC-ML is provided as evaluation IP core that does not require a license. The evaluation IP core has a 1 hour timeout built-in such that the display output freezes after the timer expires. The pre-built bitstreams and boot images are built from a full logiCVC-ML IP core.

1.3 Design Files

Download

Download and unzip the reference design archive file xapp1231-partial-reconfig-hw-accelerator-vivado.zip to a local directory.

Directory Structure

The following files are inside the xapp1231-partial-reconfig-hw-accelerator-vivado top-level directory:

• doc -- Readme and License files

• hardware -- Hardware sources

  • vivado_hls -- Vivado HLS projects for image filters

    • fast_corners -- FAST

    • sobel -- Sobel

    • simple_posterize -- Posterize

  • vivado_pr -- Vivado Partial Reconfiguration project-less design scripts

  • vivado_trd -- Vivado IP Integrator project for Zynq Base TRD

• ready_to_test -- Pre-built SD card image

• software -- Software sources

  • boot -- Zynq boot image sources

  • petalinux -- PetaLinux board support package (BSP)

  • pre-built -- Pre-built Linux open-source libraries, binaries and headers

  • xsdk -- XSDK projects

    • filter_lib -- HLS image filter library

    • perfmon_lib -- AXI performance monitor library

    • video_cmd -- Command line application

    • video_lib -- Xilinx Video library

    • video_qt -- GUI application based on Qt framework

The xapp1231-partial-reconfig-hw-accelerator-vivado directory is the starting point for each of the below tutorials.

1.4 Known Issues

See Known Issues section on Zynq Base TRD wiki.

2 Running the Reference Design