This wiki page complements the 2018.1 version of the VCU TRD.

Change Log:

• Updated all projects, IPs, and tools versions to 2018.1

• New configurable demo mode (GUI)

• Various fixes and clean-up

The Zynq® UltraScale+™ MPSoC video codec unit (VCU) targeted reference design (TRD) is an embedded video encoding/decoding application partitioned between the SoC processing system (PS), video codec unit , and programmable logic (PL) for optimal performance. The below figure shows the TRD block diagram. It consists of four designs which are highlighted in four colors. The remaining blocks are common to all designs.

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The primary goal of this TRD is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components. The TRD consists of two designs. The light turquoise colored blocks are part of the main design and lavender colored blocks are part of SDI design. The remaining blocks are common to both designs.

The design supports the following video interfaces:

Sources:

• Test pattern generator (TPG) implemented in the PL.

• HDMI-Rx capture pipeline implemented in the PL.

• MIPI CSI-2 Rx capture pipeline implemented in the PL.

• File source (SD card, USB storage, SATA hard disk).

• SDI-Rx capture pipeline implemented in the PL.

Sinks:

• DP Tx display pipeline in the PS.

• HDMI-Tx display pipeline implemented in the PL.

• SDI-Tx display pipeline implemented in the PL.

This tutorial contains information about:

• How to set up the ZCU106 evaluation board and run the reference design.

• How to build all the TRD components based on the provided source files via detailed step-by-step tutorials.

Additional material that is not hosted in the tutorial:

• Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture, and hardware architecture.

Required:

• ZCU106 evaluation board (rev B or newer) with power cable

• Monitor with DisplayPort/HDMI input supporting 3840x2160 resolution

• Display Port cable (DP certified)

• HDMI cable

• Class-10 SD card

• GooBang Doo ABOX 2017 player with the resolution set to 4KP30, color space to VUY24 and HDMI cable

• NVIDIA SHIELD Pro

• USB mouse

• Ethernet cable

• SDI Receiver - Black Magic Teranex Mini HDMI to 12G converter

• SDI Transmitter - Black Magic Teranex Mini 12G to HDMI converter

Optional:

• USB pen drive formatted with FAT32 file system and hub

• SATA drive formatted with FAT32 file system, external power supply, and data cable

• LI-IMX274MIPI-FMC image sensor daughter card

Required:

• Linux host machine for all tool flow tutorials (see UG1144 for detailed OS requirements)

• PetaLinux Tools version 2018.1 (see UG1144 for installation instructions)

• Git distributed version control system

• Silicon Labs quad CP210x USB-to-UART bridge driver

• Serial terminal emulator e.g. teraterm

• Reference Design Zip File

  • ZCU106 rev B or newer: including all source code and project files.

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

• Video Test Pattern Generator (TPG) - Free License but must be downloaded

• Video Timing controller (VTC) - Free License but must be downloaded

• Video Mixer- Purchase license - Free License but must be downloaded

• Video PHY Controller - Included with Vivado

• HDMI-Rx/Tx Subsystem - Purchase license (Hardware evaluation available)

• Video Processing Subsystem (VPSS) - Free License but must be downloaded

• MIPI CSI Controller Subsystems (mipi_csi2_rx_subsystem)- Purchase license (Hardware evaluation available)

• SDI- Rx/Tx Subsystem - Included with Vivado

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

• AR# 44029 - Licensing - LogiCORE IP Core licensing questions?

• Xilinx Licensing FAQ

• LogiCORE IP Project License Terms

The reference design has been tested successfully with the following user-supplied components.

DisplayPort Monitor:

HDMI Monitor:

HDMI Input Sources:

• GooBang Doo ABOX 2017 player with the resolution set to 4KP30, color space to VUY24 and HDMI cable

• NVIDIA SHIELD Pro

DisplayPort Cable:

• Cable Matters DisplayPort Cable-E342987

• Monster Advanced DisplayPort Cable-E194698

• HDMI 2.0 compatible cable

The TRD consists of four designs which are highlighted in four colors as shown in the above figure.

• DM1 - PL HDMI Video Capture

• DM2 - PL SDI Video Capture

• DM3 - PL SDI Video Capture and SDI Display

• DM4 – Full-fledged VCU TRD

Table below shows for each design module (row) which other module (column) it builds upon or is a combination of.

This TRD design has been tested on Rev B, Rev C, and Rev 1.0 ZCU106 evaluation boards with Production silicon. The following design files can be downloaded from here.

• Production silicon : rdf0428-zcu106-vcu-trd-2018-1.zip (NOTE: Will work on ES2 and Production Silicon.)

The TRD package is released with the source code, Vivado project, petalinux project, and SD card image that enables you to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.

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For the individual tutorials, follow the links below

• DM1 - PL HDMI Video Capture

• DM2 - PL SDI Video Capture

• DM3 - PL SDI Video Capture and SDI Display

• DM4 – Full-fledged VCU TRD

The table below lists the available hardware projects and the script used to generate them in the scripts folder.

• Observing block noise with CBR at lower bitrates(<30Mbps with AVC and < 10Mbps with HEVC).

  • Frequency: Always

  • Workaround: None.

• Observing frame drops in 4kp60 AVC 60Mbps with CBR rate control mode.

  • Frequency: Always

  • Workaround: None.

• Reduced/sub-frame latency mode is not fully functional. Observing frame drops and pipeline doesn't exit gracefully.

  • Frequency: Always

  • Workaround: None

• TPG is not supported in the 1080p pipeline.

  • Frequency: Always

  • Workaround: None

• Stopping record pipeline early then time limit will create an invalid stream.

  • Frequency: Always

  • Workaround: Run the record pipeline till time limit

• Rate control: VBR/Low-latency and latency-mode : reduced/sub-frame latency is disabled from GUI.

  • Frequency: Always

  • Workaround: From command line application user can give above options

• Observing flickering, block noise and frame drop with VBR and low-latency rate control mode from command line(from GUI it disabled ).

  • Frequency: Always

  • Workaround: None

• Observing image overlapping with SDI pipeline(SDIRx+VCU+SDITx) at 4kp60.

  • Frequency: Always

  • Workaround: run the command: killall -9 modetest , then run the “$ source /media/card/autostart.sh”

• SDI-Tx link up issue is observed after booting in SDI design.

  • Frequency: Rare

  • Workaround: Re-launch the modetest by running “$ source /media/card/autostart.sh” from command line.

• In this release, TRD supports 4kp and 1080p resolutions output sink. SDI works in 4kp output sink only.

• All VCU parameters are not exposed at GStreamer.

• This design is validated with HDMI sources (ABOX/Nvidia shield Pro) and DP/HDMI-Tx monitors that are mentioned earlier in compatibility section.

• In HEVC/AVC, max supported bitrate is 60Mbps for a single pipeline.

• With 4kp60 bandwidth (means 1-4kp60, 2-4kp30 or 4-1080p60 pipelines) b-frames should be 0, l2-cache should be enabled, gop-mode should be either basic or low_delay_p and aggregate bitrate should be 60Mbps due to bandwidth constraints.

• TRD is tested only with MONOPRICE 1x4HDMI Splitter which works till 4kp30.

• This design is validated with Teranex Mini HDMI to SDI 12G and SDI to HDMI 12G ,that are mentioned earlier in compatibility section.

• Support for only Single stream playback from the command line is available with SDI Design.

To obtain technical support for this reference design, go to the:

• Xilinx Answers Database to locate answers to known issues

• Xilinx Community Forums to ask questions or discuss technical details and issues. Please make sure to browse the existing topics first before filing a new topic. If you do file a new topic, make sure it is filed in the sub-forum that best describes your issue or question e.g. Embedded Linux for any Linux related questions. Please include "ZCU106 VCU TRD" and the release version in the topic name along with a brief summary of the issue.