{"type":"doc","content":[{"type":"paragraph","content":[{"text":"This document describes the base set of hardware required for OpenAMP to operate successfully as presented in Xilinx Vitis OpenAMP and libmetal template examples.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Table of Contents","type":"text"}]},{"type":"extension","attrs":{"layout":"default","extensionType":"com.atlassian.confluence.macro.core","extensionKey":"toc","parameters":{"macroParams":{"exclude":{"value":"Table of Contents"}},"macroMetadata":{"macroId":{"value":"4da5cc6f-f4a9-4767-a375-ef9c9f6e3bb3"},"schemaVersion":{"value":"1"},"title":"Table of Contents"}},"localId":"b1a4bfc7-8a7a-4043-b84c-08df67a1de41"}},{"type":"heading","attrs":{"level":1},"content":[{"text":"Introduction","type":"text"}]},{"type":"paragraph","content":[{"text":"This document describes the base set of hardware required for OpenAMP to operate successfully as presented in Xilinx Vitis OpenAMP and libmetal template examples. It covers configurations for the RPU memory, shared memory for both the APU and RPU, generic interrupt controllers (GIC) and the inter-processor interconnect (IPI) interrupts. There are several examples of using Vitis, PetaLinux and OpenAMP, however this is not a tutorial for these tools. The reader is encouraged to refer to Xilinx user guides listed in the ","type":"text"},{"text":"Related Links","type":"text","marks":[{"type":"link","attrs":{"href":"#Related-Links"}}]},{"text":".","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"OpenAMP on Xilinx SoCs","type":"text"}]},{"type":"mediaSingle","attrs":{"layout":"wrap-right"},"content":[{"type":"media","attrs":{"width":348,"id":"dd148409-9458-4845-80e3-d72244d75618","collection":"contentId-1837006921","type":"file","height":286}}]},{"type":"paragraph","content":[{"text":"Xilinx SoC products combine a set of heterogeneous hardware designs into one powerful and flexible platform that includes Arm Cortex-Ax, Cortex-R5 and Xilinx MicroBlaze processors. The OpenAMP project enables a distributed software architecture across this asymmetric multiprocessing platform (AMP).","type":"text"}]},{"type":"paragraph","content":[{"text":"There are two components of the OpenAMP framework:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Life Cycle Management (LCM)","type":"text","marks":[{"type":"strong"}]},{"text":" : enables a master processor to load, start and stop a firmware on a remote processor.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Inter-Processor Communication (IPC)","type":"text","marks":[{"type":"strong"}]},{"text":": interrupts, shared memory and message passing between the master and the remote processor.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Both the LCM and the IPC in the demos are using the ","type":"text"},{"text":"remoteproc","type":"text","marks":[{"type":"strong"}]},{"text":" and the ","type":"text"},{"text":"rpmsg","type":"text","marks":[{"type":"strong"}]},{"text":" drivers in the Linux kernel. Xilinx SoCs based systems should provide access to a specific set of hardware resources in order to use the OpenAMP framework. Depending on the OpenAMP or libmetal demo this includes:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Processing cores; need at least two:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"application processing unit (APU)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"real-time processing unit (RPU) for Versal and ZynqMP","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Memory for the processing system (PS): APU (master), RPU (remote) and shared memory:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"DDR","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Tightly-coupled memory (TCM)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"On-chip memory (OCM)","type":"text"}]}]}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Interrupts:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"APU GIC interrupts","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"RPU GIC interrupts","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"IPI interrupts","type":"text"}]}]}]}]}]},{"type":"paragraph","content":[{"text":"The next section tries to generalize each hardware component as it is used in the OpenAMP, followed by specific example of configuring some demos with the default values and another section showing how to change the defaults.","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Zynq UltraScale+ MPSoC and Versal","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"LCM: Memory for RPU Firmware","type":"text"}]},{"type":"paragraph","content":[{"text":"Most demos use the DDR or the Tightly Coupled Memory (TCM) for RPU firmware text and data depending on the linker script (e.g.: ","type":"text"},{"text":"linker_remote.ld","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/system/generic/machine/zynqmp_r5/linker_remote.ld"}}]},{"text":") while the stack, heap and the interrupt vector table are in the TCM. The RPU is configured to enable the TCM interfaces from reset with base address 0 for TCMA. The Linux remoteproc driver on the APU will preload the TCMA with the boot code while the RPU is halted. When the halt is removed the RPU starts fetching instructions from the reset vector address in the normal way. The RPU's firmware .vectors section is loaded into TCMA at address 0 (see linker script). It starts with a set of branch instructions called _vector_table and a few code blocks labeled _boot, init and a function Init_MPU(). When the remoteproc driver requests RPU start the execution begins at address 0 in TCMA with a jump to _boot which calls Init_MPU(). All this is fetched from and executed in the TCMA. At the end the _boot jumps to _startup which could be in the DDR. The _startup prepares the \"C runtime\" and calls main().","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"f1df54be-9d77-4a1a-be0c-db645db67c0c"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[178.0]},"content":[{"type":"paragraph","content":[{"text":"Firmware load memory","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[582.0]},"content":[{"type":"paragraph","content":[{"text":"ZynqMP / Versal","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[178.0]},"content":[{"type":"paragraph","content":[{"text":"RPU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[582.0]},"content":[{"type":"paragraph","content":[{"text":"0x3ED0_0000, see linker script","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[178.0]},"content":[{"type":"paragraph","content":[{"text":"APU kernel DT","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[582.0]},"content":[{"type":"paragraph","content":[{"text":"0x3ED0_0000, see rproc_0_reserved in the Linux Device Tree ","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[178.0]},"content":[{"type":"paragraph","content":[{"text":"APU app","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[582.0]},"content":[{"type":"paragraph","content":[{"text":"not used","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"IPC: Shared Memory","type":"text"}]},{"type":"paragraph","content":[{"text":"The OpenAMP demos have a .resource_table ELF section as in this example ","type":"text"},{"text":"linker_remote.ld","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/system/generic/machine/zynqmp_r5/linker_remote.ld"}}]},{"text":". It has list of system resources required by the Linux remoteproc, e.g.: virtIO device data used by rpmsg, see ","type":"text"},{"text":"rsc_table.h","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/machine/zynqmp_r5/rsc_table.h"}}]},{"text":" and ","type":"text"},{"text":"rsc_table.c","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/machine/zynqmp_r5/rsc_table.c"}}]},{"text":".","type":"text"}]},{"type":"paragraph","content":[{"text":"The default location for shared memory is the DDR.","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"b3b64d62-2c23-4800-a34c-f34bf53b536e"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"SHM_BASE_ADDR","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[568.0]},"content":[{"type":"paragraph","content":[{"text":"ZynqMP / Versal","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"RPU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[568.0]},"content":[{"type":"paragraph","content":[{"text":"E.g. 0x3ED8_0000, see metal_dev_table, SHARED_MEM_PA, SHARED_MEM_SIZE, SHARED_BUF_OFFSET","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"APU kernel DT","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[568.0]},"content":[{"type":"paragraph","content":[{"text":"E.g. 0x3ED8_0000, see reserved-memory nodes in the Linux Device Tree ","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"APU app: libmetal_amp_demo","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[568.0]},"content":[{"type":"paragraph","content":[{"text":"UIO nodes names for zynqMP:","type":"text"}]},{"type":"codeBlock","attrs":{"language":"none"},"content":[{"text":"SHM_DEV_NAME \"3ed80000.shm\"\nIPI_DEV_NAME=\"ff340000.ipi\" (if Versal=) \"ff360000.ipi\"\nTTC_DEV_NAME=\"ff110000.timer\" (if Versal=) \"ff0e0000.ttc0\"","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"APU app: openamp demos","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[568.0]},"content":[{"type":"codeBlock","content":[{"text":"/sys/bus/rpmsg/devices/virtio0.rpmsg-openamp-demo-channel.-1.0","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"IPC: Interrupts","type":"text"}]},{"type":"panel","attrs":{"panelType":"info"},"content":[{"type":"paragraph","content":[{"text":"Recommended Reading","type":"text","marks":[{"type":"strong"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":" ","type":"text"},{"text":"UG1085","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf"}}]},{"text":" Chapter 13: Interrupts","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":" ","type":"text"},{"text":"Versal-ACAP-TRM","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf"}}]},{"text":" Chapter 52: Inter-Processor Interrupts","type":"text"}]}]}]}]},{"type":"paragraph","content":[{"text":"The OpenAMP and Libmetal demos use the IPI interrupts to enable one processor (source agent) to interrupt another processor (destination agent). The communications process uses the IPI interrupt register structure, the system interrupt structure, and the IPI message buffers. On the RPU’s firmware side these are represented by the struct metal_device ","type":"text"},{"text":"ipi_device","type":"text","marks":[{"type":"strong"}]},{"text":" and IPI_CHN_BITMASK in ","type":"text"},{"text":"platform_info.c","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/machine/zynqmp_r5/platform_info.c"}}]},{"text":".","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"3cc0a047-5895-4fac-836c-fa949fe2e17d"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[94.0]},"content":[{"type":"paragraph","content":[{"text":"GIC","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[666.0]},"content":[{"type":"paragraph","content":[{"text":"IRQ System Interrupts: see ","type":"text"},{"text":"IPI_IRQ_VECT_ID","type":"text","marks":[{"type":"strong"}]}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[94.0]},"content":[{"type":"paragraph","content":[{"text":"Versal","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[666.0]},"content":[{"type":"paragraph","content":[{"text":"63 See \"IRQ System Interrupts\" in ","type":"text"},{"text":"Versal-ACAP-TRM","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf"}}]},{"text":" for IPI1 \"IPI 1 interrupt\";","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[94.0]},"content":[{"type":"paragraph","content":[{"text":"ZynqMP","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[666.0]},"content":[{"type":"paragraph","content":[{"text":"65 or XPAR_XIPIPSU_0_INT_ID See \"system interrupts\" in ","type":"text"},{"text":"UG1085","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf"}}]},{"text":" for RPU0 IPI_Ch1 ","type":"text"}]}]}]}]},{"type":"paragraph","content":[{"text":"The demos need two IPI channels (and IPI masks) one for the APU and one for the RPU. These are selected from the set of seven reprogrammable IPIs. Other system users might be requesting IPI channels. Both the firmware and the Linux device tree should be checked to detect and avoid conflicts.","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"8f2e3b24-52fd-4d4b-a21d-a3c3276c0a3f"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[57.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"ZynqMP","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[76.0]},"content":[{"type":"paragraph","content":[{"text":"IPI Channel","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[82.0]},"content":[{"type":"paragraph","content":[{"text":"Base Addr","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":2,"rowspan":1,"colwidth":[105.0,93.0]},"content":[{"type":"paragraph","content":[{"text":"IPI_MASK / IPI_CHN_BITMASK","type":"text"}]},{"type":"paragraph","content":[{"text":"See ","type":"text"},{"text":"UG1087 Register Reference","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html"}}]}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[347.0]},"content":[{"type":"paragraph","content":[{"text":"References","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[76.0]},"content":[{"type":"paragraph","content":[{"text":"Send to Ch_7","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[105.0]},"content":[{"type":"paragraph","content":[{"text":"Send to Ch_1","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[57.0]},"content":[{"type":"paragraph","content":[{"text":"RPU_0","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[76.0]},"content":[{"type":"paragraph","content":[{"text":"Ch_1","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[82.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF31_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[105.0]},"content":[{"type":"paragraph","content":[{"text":"0x0100_0000 (set bit 24)","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[93.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[347.0]},"content":[{"type":"paragraph","content":[{"text":"ipi_device, IPI_BASE_ADDR, IPI_CHN_BITMASK in ","type":"text"},{"text":"platform_info.h","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/machine/zynqmp_r5/platform_info.h"}}]}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[57.0]},"content":[{"type":"paragraph","content":[{"text":"APU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[76.0]},"content":[{"type":"paragraph","content":[{"text":"Ch_7","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[82.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF34_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[105.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[93.0]},"content":[{"type":"paragraph","content":[{"text":"0x100 (set bit 8)","type":"text"}]},{"type":"paragraph","content":[{"type":"hardBreak"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[347.0]},"content":[{"type":"paragraph","content":[{"text":"\"xlnx,ipi-id\" property, zynqmp_ipi1 node in ZynqMP .dtsi :","type":"text"}]},{"type":"codeBlock","content":[{"text":"zynqmp_ipi1 {\n compatible = \"xlnx,zynqmp-ipi-mailbox\";\n interrupt-parent = <&gic>;\n interrupts = <0 29 4>;\n xlnx,ipi-id = <7>;\n #address-cells = <1>;\n #size-cells = <1>;\n ranges;\n\n /* APU<->RPU0 IPI mailbox controller */\n ipi_mailbox_rpu0: mailbox@ff90000 {\n reg = <0xff990600 0x20>,\n <0xff990620 0x20>,\n <0xff9900c0 0x20>,\n <0xff9900e0 0x20>;\n reg-names = \"local_request_region\",\n \"local_response_region\",\n \"remote_request_region\",\n \"remote_response_region\";\n #mbox-cells = <1>;\n xlnx,ipi-id = <1>;\n };\n};","type":"text"}]}]}]}]},{"type":"paragraph","content":[{"text":"In Versal the channel names and numbers are different, see ","type":"text"},{"text":"Versal-ACAP-TRM","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf"}}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"1705b4d0-a526-4f6e-a125-dc61376dd844"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[54.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"},{"text":"Versal","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[72.0]},"content":[{"type":"paragraph","content":[{"text":"IPI Channel","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[87.0]},"content":[{"type":"paragraph","content":[{"text":"Base Addr","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":2,"rowspan":1,"colwidth":[95.0,90.0]},"content":[{"type":"paragraph","content":[{"text":"IPI_MASK / IPI_CHN_BITMASK","type":"text"}]},{"type":"paragraph","content":[{"text":"Versal Adaptive SoC Register Reference","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html"}}]}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[362.0]},"content":[{"type":"paragraph","content":[{"text":"References","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[72.0]},"content":[{"type":"paragraph","content":[{"text":"Send to ipi3","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[95.0]},"content":[{"type":"paragraph","content":[{"text":"Send to ipi1","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[54.0]},"content":[{"type":"paragraph","content":[{"text":"RPU_0","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[72.0]},"content":[{"type":"paragraph","content":[{"text":"ipi1","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[87.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF34_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[95.0]},"content":[{"type":"paragraph","content":[{"text":"0x20 (set bit 5)","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[90.0]},"content":[{"type":"paragraph"}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[362.0]},"content":[{"type":"paragraph","content":[{"text":"ipi_device, IPI_BASE_ADDR, IPI_CHN_BITMASK in ","type":"text"},{"text":"platform_info.h","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/OpenAMP/open-amp/blob/master/apps/machine/zynqmp_r5/platform_info.h"}}]}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[54.0]},"content":[{"type":"paragraph","content":[{"text":"APU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[72.0]},"content":[{"type":"paragraph","content":[{"text":"ipi3","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[87.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF36_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[95.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[90.0]},"content":[{"type":"paragraph","content":[{"text":"0x8 (set bit 3)","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[362.0]},"content":[{"type":"paragraph","content":[{"text":"\"xlnx,ipi-id\" property, zynqmp_ipi1 node in Versal .dtsi. The mapping of ipi-id to channel is not obvious and it’s not the same as in ZynqMP.","type":"text"}]},{"type":"codeBlock","content":[{"text":"zynqmp_ipi1 {\n compatible = \"xlnx,zynqmp-ipi-mailbox\";\n interrupt-parent = <&gic>;\n interrupts = <0 33 4>;\n xlnx,ipi-id = <5>;\n #address-cells = <1>;\n #size-cells = <1>;\n ranges;\n\n /* APU<->RPU0 IPI mailbox controller */\n ipi_mailbox_rpu0: mailbox@ff990600 {\n reg = <0xff3f0ac0 0x20>,\n <0xff3f0ae0 0x20>,\n <0xff3f0740 0x20>,\n <0xff3f0760 0x20>;\n reg-names = \"local_request_region\",\n \"local_response_region\",\n \"remote_request_region\",\n \"remote_response_region\";\n #mbox-cells = <1>;\n xlnx,ipi-id = <3>;\n };\n};","type":"text"}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"Build and Run Demos","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Build RPU firmware","type":"text"}]},{"type":"paragraph","content":[{"text":"Step 1","type":"text","marks":[{"type":"strong"}]},{"text":". Launch Vitis IDE and select a workspace directory with enough free space and fast access. Local disk is prefered as some NFS can be slow.","type":"text"}]},{"type":"paragraph","content":[{"text":"Step 2","type":"text","marks":[{"type":"strong"}]},{"text":". Create a new application project using \"File > New Application Project\". This will start a wizard that will guide you through the process.","type":"text"}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Create a new platform from hardware description XSA file. Select from the included XSA’s or use browse and import your own XSA.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Specify the application project name. E.g.: ","type":"text"},{"text":"lm_amp","type":"text","marks":[{"type":"strong"}]},{"text":" and select psu_cortexr5_0 as the target processor from the list.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Select template for your project, e.g. \"Libmetal AMP Application\" and click \"Finish\":","type":"text"}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"754185bc-632c-44b1-9217-8c3075b99ad0"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[254.0]},"content":[{"type":"paragraph","content":[{"text":"Processor for the RPU firmware project ","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"paragraph","content":[{"text":"Domain: FreeRTOS or generic","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"paragraph","content":[{"text":"Libmetal AMP Demo, OpenAMP echo-test,..","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[254.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":805,"id":"421a356d-7ef1-49c2-870a-1e52f6a52ae5","collection":"contentId-1837006921","type":"file","height":778}}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":805,"id":"ba345de6-2275-4c88-be92-1d6572d519f9","collection":"contentId-1837006921","type":"file","height":534}}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":805,"id":"dced5a04-be45-4ef8-b3de-b362d4ec6f33","collection":"contentId-1837006921","type":"file","height":589}}]}]}]}]},{"type":"paragraph","content":[{"text":"Configuration of some hardware blocks used in this demo must match between the RPU’s firmware and APU’s Linux kernel, device tree and the user application. Please, see the \"Hardware specification\" tab to examine the address maps for APU and RPU processors:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Memory: DDR and Tightly-coupled memory (TCM)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Interrupts: PS-to-PS interrupts and Inter-processor interrupts (IPI)","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Timers: Triple Timer Counters (TTC)","type":"text"}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"f3e1bfdd-b5b6-4510-bc70-4d7d6f5bf2bf"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[254.0]},"content":[{"type":"paragraph","content":[{"text":"Hardware specification: Memory Maps","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"paragraph","content":[{"text":"IPI: psu_ipi_1 example","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"paragraph","content":[{"text":"Linker Script: lscript.ld","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[254.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":1051,"id":"daa9e2ce-410b-4103-8ef1-b294d6274948","collection":"contentId-1837006921","type":"file","height":677}}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":854,"id":"145f7b69-8629-4473-be57-2577e3e2b344","collection":"contentId-1837006921","type":"file","height":834}}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[253.0]},"content":[{"type":"mediaSingle","attrs":{"layout":"center"},"content":[{"type":"media","attrs":{"width":950,"id":"4bcbdc18-eb50-4b45-bd68-bbb24215765a","collection":"contentId-1837006921","type":"file","height":670}}]}]}]}]},{"type":"paragraph","content":[{"text":"Firmware memory map: Select ","type":"text"},{"text":"lscript.ld","type":"text","marks":[{"type":"strong"}]},{"text":" file in the source Explorer. The summary view shows the memory regions for this application:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The processor is configured to enable the TCM interfaces from reset with base address 0x0 for TCMA and 0x20000 for TCMB. This demo does not use TCMB.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The stack, heap and the interrupt vector table are in psu_r5_atcm_MEM_0, TCMA.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The text, read-only, initialized, uninitialized data sections, etc. are in psu_r5_ddr_0_MEM_0 starting at 0x3ED00000 with LENGTH=0x80000.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"OpenAMP demos have .resource_table ELF section. It has list of system resources required by the Linux remoteproc, e.g.: virtIO device data.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The Linux remoteproc driver on the APU will preload the TCMA with the boot code while halting the RPU via nCPUHALTm pin. When the nCPUHALTm pin is deasserted, the processor starts fetching instructions from the reset vector address in the normal way. The FreeRTOS _vector_table is loaded into TCMA at address 0x0 followed by _boot and Init_MPU().","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The execution starts at address 0x0 in TCMA via a jump to _boot which calls Init_MPU(). All this is fetched from and executed in the TCMA. At the end the _boot jumps to _startup in the DDR. The _startup prepares the \"C runtime\" and calls main(). Starting from _startup the RPU fetches its instructions from the DDR while its stack and heap are in the TCMA.","type":"text"}]}]}]},{"type":"paragraph","content":[{"text":"Step 3.","type":"text","marks":[{"type":"strong"}]},{"text":" Build the application project: click lm_amp or lm_amp_system in the source Explorer and select \"Project > Build Project\". The build produces an ARM CortexR5 binary in the Debug (or Release) directory called lm_amp.elf. In this example this binary will be loaded to execute on the RPU (r5_0) via Xilinx remoteproc Linux driver.","type":"text"}]},{"type":"heading","attrs":{"level":3},"content":[{"text":"Build PetaLinux","type":"text"}]},{"type":"paragraph","content":[{"text":"Create a PetaLinux project using the BSP where we took the XSA file for the RPU firmware:","type":"text"}]},{"type":"orderedList","attrs":{"order":1},"content":[{"type":"listItem","content":[{"type":"codeBlock","content":[{"text":" source \n petalinux-create -t project -s ","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Depending on the selected demo you have to enable the following kernel config options (see: project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend and the kernel config file (e.g.: defconfig) it includes):","type":"text"}]},{"type":"codeBlock","content":[{"text":"CONFIG_UIO_PDRV_GENIRQ=m\nCONFIG_RPMSG_CHAR=m\nCONFIG_RPMSG_VIRTIO=m\nCONFIG_RPMSG=m\nCONFIG_VIRTIO=m\nCONFIG_REMOTEPROC=y\nCONFIG_ZYNQMP_R5_REMOTEPROC=m\nCONFIG_SPARSEMEM_VMEMMAP=y","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Copy one of the following device tree overlay files into ","type":"text"},{"text":"/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi","type":"text","marks":[{"type":"code"}]},{"text":" depending on the demo selected for the RPU firmware:","type":"text"}]}]}]},{"type":"layoutSection","content":[{"type":"layoutColumn","attrs":{"width":50.0},"content":[{"type":"expand","attrs":{"title":"Libmetal AMP demo: system-user.dtsi for ZynqMP"},"content":[{"type":"codeBlock","content":[{"text":"/ {\n reserved-memory {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n rproc_0_reserved: rproc@3ed000000 {\n no-map;\n reg = <0x0 0x3ed00000 0x0 0x40000>;\n };\n };\n\n zynqmp-rpu {\n compatible = \"xlnx,zynqmp-r5-remoteproc-1.0\";\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n core_conf = \"lockstep\";\n reg = <0x0 0xFF9A0000 0x0 0x10000>;\n r5_0: r5@0 {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n memory-region = <&rproc_0_reserved>;\n pnode-id = <0x7>;\n tcm_0_a: tcm_0@0 {\n reg = <0x0 0xFFE00000 0x0 0x10000>;\n pnode-id = <0xf>;\n };\n tcm_0_b: tcm_0@1 {\n reg = <0x0 0xFFE20000 0x0 0x10000>;\n pnode-id = <0x10>;\n };\n };\n };\n /* Shared memory */\n shm0: shm@0 {\n compatible = \"shm\";\n reg = <0x0 0x3ed80000 0x0 0x1000000>;\n };\n /* IPI device */\n ipi0: ipi@0 {\n compatible = \"ipi_uio\";\n reg = <0x0 0xff340000 0x0 0x1000>;\n interrupt-parent = <&gic>;\n interrupts = <0 29 4>;\n };\n};\n\n&ttc0 {\n /* compatible = \"ttc\"; timer@ff110000 */\n status = \"okay\";\n};\n&ttc1 {\n /* compatible = \"ttc\"; timer@ff120000 */\n status = \"okay\";\n};","type":"text"}]}]}]},{"type":"layoutColumn","attrs":{"width":50.0},"content":[{"type":"expand","attrs":{"title":"Libmetal AMP demo: system-user.dtsi for Versal"},"content":[{"type":"codeBlock","content":[{"text":"/ {\n reserved-memory {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n rproc_0_reserved: rproc@3ed000000 {\n no-map;\n reg = <0x0 0x3ed00000 0x0 0x2000000>;\n };\n };\n\n zynqmp-rpu {\n compatible = \"xlnx,zynqmp-r5-remoteproc-1.0\";\n #address-cells = <0x2>;\n #size-cells = <0x2>;\n ranges;\n core_conf = \"lockstep\";\n reg = <0x0 0xff9a0000 0x0 0x10000>;\n\n r5_0: r5@0 {\n #address-cells = <0x2>;\n #size-cells = <0x2>;\n ranges;\n memory-region = <&rproc_0_reserved>;\n pnode-id = <0x18110005>;\n tcm_0@0 {\n reg = <0x0 0xffe00000 0x0 0x10000>;\n pnode-id = <0x1831800b>;\n };\n\n tcm_0@1 {\n reg = <0x0 0xffe20000 0x0 0x10000>;\n pnode-id = <0x1831800c>;\n };\n };\n };\n\n /* Shared memory */\n shm0: shm@0 {\n compatible = \"shm_uio\";\n reg = <0x0 0x3ed80000 0x0 0x1000000>;\n };\n\n /* IPI device */\n ipi_amp: ipi@ff360000 {\n compatible = \"ipi_uio\";\n reg = <0x0 0xff360000 0x0 0x1000>;\n interrupt-parent = <&gic>;\n interrupts = <0 33 4>;\n };\n\n ttc0 {\n compatible = \"ttc-uio\";\n reg = <0x0 0xFF0E0000 0x0 0x1000>;\n };\n};","type":"text"}]}]}]}]},{"type":"layoutSection","content":[{"type":"layoutColumn","attrs":{"width":50.0},"content":[{"type":"expand","attrs":{"title":"OpenAMP demos: system-user.dtsi for ZynqMP"},"content":[{"type":"codeBlock","content":[{"text":"/ {\n reserved-memory {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 {\n no-map;\n reg = <0x0 0x3ed40000 0x0 0x4000>;\n };\n rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 {\n no-map;\n reg = <0x0 0x3ed44000 0x0 0x4000>;\n };\n rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 {\n no-map;\n reg = <0x0 0x3ed48000 0x0 0x100000>;\n };\n rproc_0_reserved: rproc@3ed00000 {\n no-map;\n reg = <0x0 0x3ed00000 0x0 0x40000>;\n };\n };\n\n zynqmp-rpu {\n compatible = \"xlnx,zynqmp-r5-remoteproc-1.0\";\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n core_conf = \"lockstep\";\n reg = <0x0 0xFF9A0000 0x0 0x10000>;\n r5_0: r5@0 {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;\n pnode-id = <0x7>;\n mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;\n mbox-names = \"tx\", \"rx\";\n tcm_0_a: tcm_0@0 {\n reg = <0x0 0xFFE00000 0x0 0x10000>;\n pnode-id = <0xf>;\n };\n tcm_0_b: tcm_0@1 {\n reg = <0x0 0xFFE20000 0x0 0x10000>;\n pnode-id = <0x10>;\n };\n };\n };\n\n zynqmp_ipi1 {\n compatible = \"xlnx,zynqmp-ipi-mailbox\";\n interrupt-parent = <&gic>;\n interrupts = <0 29 4>;\n xlnx,ipi-id = <7>;\n #address-cells = <1>;\n #size-cells = <1>;\n ranges;\n\n /* APU<->RPU0 IPI mailbox controller */\n ipi_mailbox_rpu0: mailbox@ff90000 {\n reg = <0xff990600 0x20>,\n <0xff990620 0x20>,\n <0xff9900c0 0x20>,\n <0xff9900e0 0x20>;\n reg-names = \"local_request_region\",\n \"local_response_region\",\n \"remote_request_region\",\n \"remote_response_region\";\n #mbox-cells = <1>;\n xlnx,ipi-id = <1>;\n };\n };\n};","type":"text"}]}]}]},{"type":"layoutColumn","attrs":{"width":50.0},"content":[{"type":"expand","attrs":{"title":"OpenAMP demos: system-user.dtsi for Versal"},"content":[{"type":"codeBlock","content":[{"text":" / {\n reserved-memory {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n rpu0vdev0vring0: rpu0vdev0vring0@3ed40000 {\n no-map;\n reg = <0x0 0x3ed40000 0x0 0x4000>;\n };\n rpu0vdev0vring1: rpu0vdev0vring1@3ed44000 {\n no-map;\n reg = <0x0 0x3ed44000 0x0 0x4000>;\n };\n rpu0vdev0buffer: rpu0vdev0buffer@3ed48000 {\n no-map;\n reg = <0x0 0x3ed48000 0x0 0x100000>;\n };\n rproc_0_reserved: rproc@3ed00000 {\n no-map;\n reg = <0x0 0x3ed00000 0x0 0x40000>;\n };\n };\n\n zynqmp-rpu {\n compatible = \"xlnx,zynqmp-r5-remoteproc-1.0\";\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n core_conf = \"lockstep\";\n reg = <0x0 0xFF9A0000 0x0 0x10000>;\n r5_0: r5@0 {\n #address-cells = <2>;\n #size-cells = <2>;\n ranges;\n memory-region = <&rproc_0_reserved>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;\n pnode-id = <0x18110005>;\n mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;\n mbox-names = \"tx\", \"rx\";\n tcm_0_a: tcm_0@0 {\n reg = <0x0 0xFFE00000 0x0 0x10000>;\n pnode-id = <0x1831800b>;\n };\n tcm_0_b: tcm_0@1 {\n reg = <0x0 0xFFE20000 0x0 0x10000>;\n pnode-id = <0x1831800c>;\n };\n };\n };\n\n zynqmp_ipi1 {\n compatible = \"xlnx,zynqmp-ipi-mailbox\";\n interrupt-parent = <&gic>;\n interrupts = <0 33 4>;\n xlnx,ipi-id = <5>;\n #address-cells = <1>;\n #size-cells = <1>;\n ranges;\n\n /* APU<->RPU0 IPI mailbox controller */\n ipi_mailbox_rpu0: mailbox@ff990600 {\n reg = <0xff3f0ac0 0x20>,\n <0xff3f0ae0 0x20>,\n <0xff3f0740 0x20>,\n <0xff3f0760 0x20>;\n reg-names = \"local_request_region\",\n \"local_response_region\",\n \"remote_request_region\",\n \"remote_response_region\";\n #mbox-cells = <1>;\n xlnx,ipi-id = <3>;\n };\n };\n};","type":"text"}]}]}]}]},{"type":"panel","attrs":{"panelType":"note"},"content":[{"type":"paragraph","content":[{"text":"The following descriptions refer to the \"ZynqMP Libmetal AMP Demo\" device tree overlay (.dtsi).","type":"text"}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The property of the ","type":"text"},{"text":"rproc_0_reserved","type":"text","marks":[{"type":"strong"}]},{"text":" node has the same memory region as the one selected in the lscript.ld in the Vitis application. This allows Xilinx Linux remoteproc driver to take our lm_amp CortexR5 binary (from ","type":"text"},{"text":"/lib/firmware","type":"text","marks":[{"type":"code"}]},{"text":"), parse its ELF headers and set up the segments in the DDR where the RPU can read and execute the text and access the shared data.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The property of ","type":"text"},{"text":"shm0","type":"text","marks":[{"type":"strong"}]},{"text":" node is included for Linux UIO to let user space demo to talk to our firmware application lm_amp on the RPU.","type":"text"}]}]},{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Cross-reference for Shared memory: the Linux device tree (","type":"text"},{"text":"system-user.dtsi","type":"text","marks":[{"type":"code"}]},{"text":"), RPU linker script (","type":"text"},{"text":"lscript.ld","type":"text","marks":[{"type":"code"}]},{"text":"), ","type":"text"},{"text":"metal_dev_table ","type":"text","marks":[{"type":"code"}]},{"text":"from ","type":"text"},{"text":"freertos/zynqmp_r5/zynqmp_amp_demo/sys_init.c","type":"text","marks":[{"type":"code"}]}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"970b2881-a22a-46d0-9fd9-e30efafdf341"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[103.0]},"content":[{"type":"paragraph"}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[329.0]},"content":[{"type":"paragraph","content":[{"text":"firmware ELF: text, data, etc. sections","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[328.0]},"content":[{"type":"paragraph","content":[{"text":"shared memory","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[103.0]},"content":[{"type":"paragraph","content":[{"text":"RPU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[329.0]},"content":[{"type":"paragraph","content":[{"text":"lscript.ld: ORIGIN = 0x3ED00000, LENGTH = 0x00080000","type":"text"}]},{"type":"paragraph","content":[{"text":"/* 0x80000 is excessive. Can be 0x40000 as in the DT */","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[328.0]},"content":[{"type":"paragraph","content":[{"text":"SHM_BASE_ADDR 0x3ED80000","type":"text"}]},{"type":"paragraph","content":[{"text":".size = 0x1000000 /* sys_init.c metal_dev_table */","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[103.0]},"content":[{"type":"paragraph","content":[{"text":"APU kernel DT","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[329.0]},"content":[{"type":"paragraph","content":[{"text":"rproc_0_reserved: reg = <0x0 0x3ed00000 0x0 0x40000>;","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[328.0]},"content":[{"type":"paragraph","content":[{"text":"shm0: reg = <0x0 0x3ed80000 0x0 0x1000000>;","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[103.0]},"content":[{"type":"paragraph","content":[{"text":"APU app","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[329.0]},"content":[{"type":"paragraph","content":[{"text":"/* not referenced via UIO */","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[328.0]},"content":[{"type":"paragraph","content":[{"text":"SHM_DEV_NAME \"3ed80000.shm\" /* common.h */","type":"text"}]}]}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Cross-reference for the ","type":"text"},{"text":"IPI. ","type":"text","marks":[{"type":"strong"}]},{"text":"The ipi0 node for Linux UIO uses IPI Channel 7 with base address 0xFF34_0000, while the RPU uses its default IPI Channel-1 with BASE_ADDRESS 0xFF31_0000.","type":"text"}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"98c4c806-dbef-41d7-ab88-f8a1e845cde0"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[51.0]},"content":[{"type":"paragraph"}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[71.0]},"content":[{"type":"paragraph","content":[{"text":"IPI Channel","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[92.0]},"content":[{"type":"paragraph","content":[{"text":"Base Addr","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":2,"rowspan":1,"colwidth":[143.0,100.0]},"content":[{"type":"paragraph","marks":[{"type":"alignment","attrs":{"align":"center"}}],"content":[{"text":"IPI_MASK","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":2,"colwidth":[303.0]},"content":[{"type":"paragraph","content":[{"text":"References","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[71.0]},"content":[{"type":"paragraph","content":[{"text":"Send IPI to Ch_7","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[143.0]},"content":[{"type":"paragraph","content":[{"text":"Send IPI to Ch_1","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[51.0]},"content":[{"type":"paragraph","content":[{"text":"RPU_0","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[71.0]},"content":[{"type":"paragraph","content":[{"text":"Ch_1","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[92.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF31_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[143.0]},"content":[{"type":"paragraph","content":[{"text":"0x100_0000 (set bit 24)","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[100.0]},"content":[{"type":"paragraph"}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[303.0]},"content":[{"type":"paragraph","content":[{"text":"IPI_MASK 0x1000000 in common.h","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[51.0]},"content":[{"type":"paragraph","content":[{"text":"APU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[71.0]},"content":[{"type":"paragraph","content":[{"text":"Ch_7","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[92.0]},"content":[{"type":"paragraph","content":[{"text":"0xFF34_0000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[143.0]},"content":[{"type":"paragraph"}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[100.0]},"content":[{"type":"paragraph","content":[{"text":"0x100 (set bit 8)","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[303.0]},"content":[{"type":"paragraph","content":[{"text":"-DCONFIG_IPI_MASK=0x100 in CMakeLists.txt","type":"text"}]}]}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"The RPU code uses metal_dev_table from sys_init.c, common.h, CMakeLists.txt","type":"text"}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"357181f5-63da-4096-b480-edbc2501a9be"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[123.0]},"content":[{"type":"paragraph","content":[{"text":"RPU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[637.0]},"content":[{"type":"paragraph","content":[{"text":"IPI_BASE_ADDR=0xFF310000; /* metal_dev_table, CMakeLists.txt */","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[123.0]},"content":[{"type":"paragraph","content":[{"text":"APU kernel DT","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[637.0]},"content":[{"type":"paragraph","content":[{"text":"reg = <0x0 0xff340000 0x0 0x1000>; /* ipi0 node */","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[123.0]},"content":[{"type":"paragraph","content":[{"text":"APU app","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[637.0]},"content":[{"type":"paragraph","content":[{"text":"IPI_DEV_NAME=\"ff340000.ipi\" /* common.h, CMakeLists.txt */","type":"text"}]}]}]}]},{"type":"bulletList","content":[{"type":"listItem","content":[{"type":"paragraph","content":[{"text":"Cross-reference for the ","type":"text"},{"text":"TTC","type":"text","marks":[{"type":"strong"}]},{"text":"s, mapped via UIO for the Linux demo app","type":"text"}]}]}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"be127c2e-e8e8-43fe-9513-ae63200a58b4"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[124.0]},"content":[{"type":"paragraph","content":[{"text":"RPU","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[636.0]},"content":[{"type":"paragraph","content":[{"text":"TTC0_BASE_ADDR=0xFF0E0000; /* metal_dev_table, CMakeLists.txt */","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[124.0]},"content":[{"type":"paragraph","content":[{"text":"APU kernel DT","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[636.0]},"content":[{"type":"paragraph","content":[{"text":"&ttc0 /* enable TTC0 via the reference to ttc0 node */","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[124.0]},"content":[{"type":"paragraph","content":[{"text":"APU app","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[636.0]},"content":[{"type":"paragraph","content":[{"text":"TTC_DEV_NAME=\"ff110000.timer\" /* common.h, CMakeLists.txt */","type":"text"}]}]}]}]},{"type":"paragraph","content":[{"text":"Build the PetaLinux project and package the BOOT.bin for Versal","type":"text"}]},{"type":"codeBlock","content":[{"text":" petalinux-build\n petalinux-package --boot --plm --psmfw --u-boot --dtb","type":"text"}]},{"type":"paragraph","content":[{"text":"For other architectures please see ","type":"text"},{"text":"UG1144 PetaLinux Tools","type":"text","marks":[{"type":"link","attrs":{"href":"https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1144-petalinux-tools-reference-guide.pdf"}}]},{"text":".","type":"text"}]},{"type":"heading","attrs":{"level":1},"content":[{"text":"Changing the Defaults","type":"text"}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"LCM: TCM for RPU Firmware","type":"text"}]},{"type":"paragraph","content":[{"text":"Some OpenAMP demos are configured to have their text segment in the DDR memory. This allows larger firmware to run on RPU, but it might be slower compared to running from the TCM. According to Cortex-R5 Technical Reference Manual: ","type":"text"},{"text":"“A ATCM typically holds interrupt or exception code that must be accessed at high speed, without any potential delay resulting from a cache miss. A BTCM typically holds a block of data for intensive processing, such as audio or video processing.” ","type":"text","marks":[{"type":"em"}]},{"text":"Another reason to run from the TCM is power usage, i.e. if the APU decides to suspend the DDR can be powered down or put into retention mode to save power.","type":"text"}]},{"type":"paragraph","content":[{"text":"The linker script controls the location of the ELF sections of the RPU firmware. For example, to run with .vectors, .text and .note.gnu.build-id in psu_r5_atcm_MEM_0, and with everything else in psu_r5_btcm_MEM_0, use the following linker script:","type":"text"}]},{"type":"expand","attrs":{"title":"Linker script for TCM"},"content":[{"type":"table","attrs":{"layout":"default","localId":"9313beb7-8b34-4801-8d91-f96c192f800d"},"content":[{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[1248.0]},"content":[{"type":"codeBlock","content":[{"text":"_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;\n_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x4000;\n\n_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;\n_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;\n_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;\n_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;\n_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;\n\n/* Define Memories in the system */\n\nMEMORY\n{\n psu_r5_atcm_MEM_0 : ORIGIN = 0x0, LENGTH = 0x10000\n psu_r5_btcm_MEM_0 : ORIGIN = 0x20000, LENGTH = 0x10000\n psu_r5_ddr_0_MEM_0 : ORIGIN = 0x3ed00000, LENGTH = 0x80000\n}\n\n/* Specify the default entry point to the program */\n\nENTRY(_boot)\n\n/* Define the sections, and where they are mapped in memory */\n\nSECTIONS\n{\n.vectors : {\n KEEP (*(.vectors))\n *(.boot)\n} > psu_r5_atcm_MEM_0\n\n.text : {\n *(.text)\n *(.text.*)\n *(.gnu.linkonce.t.*)\n *(.plt)\n *(.gnu_warning)\n *(.gcc_execpt_table)\n *(.glue_7)\n *(.glue_7t)\n *(.vfp11_veneer)\n *(.ARM.extab)\n *(.gnu.linkonce.armextab.*)\n *(.note.gnu.build-id)\n} > psu_r5_atcm_MEM_0\n\n.note.gnu.build-id : {\n KEEP (*(.note.gnu.build-id))\n} > psu_r5_atcm_MEM_0\n\n.init : {\n KEEP (*(.init))\n} > psu_r5_btcm_MEM_0\n\n.fini : {\n KEEP (*(.fini))\n} > psu_r5_btcm_MEM_0\n\n.interp : {\n KEEP (*(.interp))\n} > psu_r5_btcm_MEM_0\n\n.note-ABI-tag : {\n KEEP (*(.note-ABI-tag))\n} > psu_r5_btcm_MEM_0\n\n.rodata : {\n __rodata_start = .;\n *(.rodata)\n *(.rodata.*)\n *(.gnu.linkonce.r.*)\n __rodata_end = .;\n} > psu_r5_btcm_MEM_0\n\n.rodata1 : {\n __rodata1_start = .;\n *(.rodata1)\n *(.rodata1.*)\n __rodata1_end = .;\n} > psu_r5_btcm_MEM_0\n\n.sdata2 : {\n __sdata2_start = .;\n *(.sdata2)\n *(.sdata2.*)\n *(.gnu.linkonce.s2.*)\n __sdata2_end = .;\n} > psu_r5_btcm_MEM_0\n\n.sbss2 : {\n __sbss2_start = .;\n *(.sbss2)\n *(.sbss2.*)\n *(.gnu.linkonce.sb2.*)\n __sbss2_end = .;\n} > psu_r5_btcm_MEM_0\n\n.data : {\n __data_start = .;\n *(.data)\n *(.data.*)\n *(.gnu.linkonce.d.*)\n *(.jcr)\n *(.got)\n *(.got.plt)\n __data_end = .;\n} > psu_r5_btcm_MEM_0\n\n.data1 : {\n __data1_start = .;\n *(.data1)\n *(.data1.*)\n __data1_end = .;\n} > psu_r5_btcm_MEM_0\n\n.got : {\n *(.got)\n} > psu_r5_btcm_MEM_0\n\n.ctors : {\n __CTOR_LIST__ = .;\n ___CTORS_LIST___ = .;\n KEEP (*crtbegin.o(.ctors))\n KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))\n KEEP (*(SORT(.ctors.*)))\n KEEP (*(.ctors))\n __CTOR_END__ = .;\n ___CTORS_END___ = .;\n} > psu_r5_btcm_MEM_0\n\n.dtors : {\n __DTOR_LIST__ = .;\n ___DTORS_LIST___ = .;\n KEEP (*crtbegin.o(.dtors))\n KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))\n KEEP (*(SORT(.dtors.*)))\n KEEP (*(.dtors))\n __DTOR_END__ = .;\n ___DTORS_END___ = .;\n} > psu_r5_btcm_MEM_0\n\n.fixup : {\n __fixup_start = .;\n *(.fixup)\n __fixup_end = .;\n} > psu_r5_btcm_MEM_0\n\n.eh_frame : {\n *(.eh_frame)\n} > psu_r5_btcm_MEM_0\n\n.eh_framehdr : {\n __eh_framehdr_start = .;\n *(.eh_framehdr)\n __eh_framehdr_end = .;\n} > psu_r5_btcm_MEM_0\n\n.gcc_except_table : {\n *(.gcc_except_table)\n} > psu_r5_btcm_MEM_0\n\n.mmu_tbl (ALIGN(16384)) : {\n __mmu_tbl_start = .;\n *(.mmu_tbl)\n __mmu_tbl_end = .;\n} > psu_r5_btcm_MEM_0\n\n.ARM.exidx : {\n __exidx_start = .;\n *(.ARM.exidx*)\n *(.gnu.linkonce.armexidix.*.*)\n __exidx_end = .;\n} > psu_r5_btcm_MEM_0\n\n.preinit_array : {\n __preinit_array_start = .;\n KEEP (*(SORT(.preinit_array.*)))\n KEEP (*(.preinit_array))\n __preinit_array_end = .;\n} > psu_r5_btcm_MEM_0\n\n.init_array : {\n __init_array_start = .;\n KEEP (*(SORT(.init_array.*)))\n KEEP (*(.init_array))\n __init_array_end = .;\n} > psu_r5_btcm_MEM_0\n\n.fini_array : {\n __fini_array_start = .;\n KEEP (*(SORT(.fini_array.*)))\n KEEP (*(.fini_array))\n __fini_array_end = .;\n} > psu_r5_btcm_MEM_0\n\n.ARM.attributes : {\n __ARM.attributes_start = .;\n *(.ARM.attributes)\n __ARM.attributes_end = .;\n} > psu_r5_btcm_MEM_0\n\n.sdata : {\n __sdata_start = .;\n *(.sdata)\n *(.sdata.*)\n *(.gnu.linkonce.s.*)\n __sdata_end = .;\n} > psu_r5_btcm_MEM_0\n\n.sbss (NOLOAD) : {\n __sbss_start = .;\n *(.sbss)\n *(.sbss.*)\n *(.gnu.linkonce.sb.*)\n __sbss_end = .;\n} > psu_r5_btcm_MEM_0\n\n.tdata : {\n __tdata_start = .;\n *(.tdata)\n *(.tdata.*)\n *(.gnu.linkonce.td.*)\n __tdata_end = .;\n} > psu_r5_btcm_MEM_0\n\n.tbss : {\n __tbss_start = .;\n *(.tbss)\n *(.tbss.*)\n *(.gnu.linkonce.tb.*)\n __tbss_end = .;\n} > psu_r5_btcm_MEM_0\n\n.bss (NOLOAD) : {\n . = ALIGN(4);\n __bss_start__ = .;\n *(.bss)\n *(.bss.*)\n *(.gnu.linkonce.b.*)\n *(COMMON)\n . = ALIGN(4);\n __bss_end__ = .;\n} > psu_r5_btcm_MEM_0\n\n_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );\n\n_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );\n\n/* Generate Stack and Heap definitions */\n\n.heap (NOLOAD) : {\n . = ALIGN(16);\n _heap = .;\n HeapBase = .;\n _heap_start = .;\n . += _HEAP_SIZE;\n _heap_end = .;\n HeapLimit = .;\n} > psu_r5_btcm_MEM_0\n\n.stack (NOLOAD) : {\n . = ALIGN(16);\n _stack_end = .;\n . += _STACK_SIZE;\n _stack = .;\n __stack = _stack;\n . = ALIGN(16);\n _irq_stack_end = .;\n . += _IRQ_STACK_SIZE;\n __irq_stack = .;\n _supervisor_stack_end = .;\n . += _SUPERVISOR_STACK_SIZE;\n . = ALIGN(16);\n __supervisor_stack = .;\n _abort_stack_end = .;\n . += _ABORT_STACK_SIZE;\n . = ALIGN(16);\n __abort_stack = .;\n _fiq_stack_end = .;\n . += _FIQ_STACK_SIZE;\n . = ALIGN(16);\n __fiq_stack = .;\n _undef_stack_end = .;\n . += _UNDEF_STACK_SIZE;\n . = ALIGN(16);\n __undef_stack = .;\n} > psu_r5_btcm_MEM_0\n\n_end = .;\n}","type":"text"}]}]}]}]}]},{"type":"heading","attrs":{"level":2},"content":[{"text":"IPC: Shared Memory","type":"text"}]},{"type":"paragraph","content":[{"text":"Shared memory parameter changes need to be coordinated between the RPU firmware code and the APU's Linux device tree as shown in this table:","type":"text"}]},{"type":"table","attrs":{"layout":"default","width":1800.0,"localId":"58e2bda5-1af6-45c4-af09-293701875bab"},"content":[{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"type":"hardBreak"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"Default","type":"text"}]}]},{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"Change to","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"RPU SHARED_MEM_PA","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"0x3ED40000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"0x3EF40000","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"RPU SHARED_MEM_SIZE","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"0x100000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"no change","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"RPU SHARED_BUF_OFFSET","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"0x8000","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"no change","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableHeader","attrs":{"colspan":1,"rowspan":1,"colwidth":[192.0]},"content":[{"type":"paragraph","content":[{"text":"Linux DT: rpu0vdev0vring0","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1,"colwidth":[284.0]},"content":[{"type":"paragraph","content":[{"text":"reg = <0x0 0x3ed40000 0x0 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