Zynq UltraScale+ MPSoC Base TRD 2019.2 - Design Module 2

Design Overview

This design module demonstrates the FreeRTOS and application running on RPU-0, where:

FreeRTOS boots on RPU-0
FreeRTOS application "heartbeat" prints periodic messages on UART-1

Design Components

petalinux_bsp
heartbeat.elf

Build Flow Tutorials

This tutorial uses both Vitis and PetaLinux tools. It is recommended to use separate shells for each of the tools.

Heartbeat Application

The heartbeat application is a FreeRTOS application that executes on RPU-0 after the FSBL has finished. This application is a simple dual task application that demonstrates communication between the two tasks by printing messages to the UART1 console.

Create a new Vitis workspace.
% cd $TRD_HOME/workspaces/ws_heartbeat % vitis -workspace . &
Click 'Import Project' from the welcome screen, Choose 'Eclipse workspace' and select next.
Uncheck 'copy projects into workspace', browse to the current working directory and make sure the heartbeat, and heartbeat_system are selected. Click Finish.
Double click on 'heartbeat_system.sprj' and close the dialog box for platform.

from the top menu tab choose 'File' → 'New platform', enter Project name as 'hw_platform_0' and select 'Next'.

Choose 'Create from hardware specification (XSA)' and browse to the xsa file in the 'hwfile' directory of 'ws_heartbeat workspace',
Select operating system as 'freertos10_xilinx' and processor as 'psu_cortexr5_0' and click Finish.

In the System Project Settings tab, Add the new custom platform generated from xsa. Click Yes on the dialog box, when prompted to change the platform.

double click on 'heartbeat.prj' in the Explorer tab, and click 'Navigate to BSP settings'

modify BSP settings for Cortexr5_0 processor

under overview panel select 'freertos10_xilinx' and modify 'stdin/stdout' to 'psu_uart_1', select ok.

Right-click on the heartbeat project and select 'Build Project'.

Copy the generated heartbeat executable into the PetaLinux BSP.
cp heartbeat/Debug/heartbeat.elf $TRD_HOME/petalinux/bsp/images/linux

PetaLinux BSP

This tutorial shows how to build a boot image that includes the heartbeat application using the PetaLinux build tool. This step assumes you have run through the PetaLinux build in DM1 previously.

Create a boot image.
% cd $TRD_HOME/petalinux/bsp/images/linux % petalinux-package --boot --bif=../../project-spec/boot/dm2.bif --force
Copy the generated boot image to the dm2 SD card directory.
% mkdir -p $TRD_HOME/sd_card/dm2 % cp BOOT.BIN $TRD_HOME/sd_card/dm2

Run Flow Tutorial

See here for board setup instructions.
Copy all the files from the $TRD_HOME/sd_card/dm2 SD card directory to a FAT formatted SD card.
Power on the board to boot the images; make sure all power rail LEDs are lit green (Note: DS1 / FPGA_INIT_B LED remains Red as there is no bit stream to configure the FPGA).
The user can now see FSBL prints on UART-0 and prints from heartbeat application can be viewed on UART-1 which is shown in the following picture:
Hello from Freertos example main Rx task (task number: 0) received string from Tx task: I am alive Rx task (task number: 1) received string from Tx task: I am alive Rx task (task number: 2) received string from Tx task: I am alive Rx task (task number: 3) received string from Tx task: I am alive Rx task (task number: 4) received string from Tx task: I am alive Rx task (task number: 5) received string from Tx task: I am alive Rx task (task number: 6) received string from Tx task: I am alive Rx task (task number: 7) received string from Tx task: I am alive Rx task (task number: 8) received string from Tx task: I am alive Rx task (task number: 9) received string from Tx task: I am alive Rx task (task number: 10) received string from Tx task: I am alive Rx task (task number: 11) received string from Tx task: I am alive Rx task (task number: 12) received string from Tx task: I am alive

Next Steps

Continue with Design Module 3.
Return to the Design Tutorials Overview.