This page provides an overview of the 2019.2 version of the Zynq UltraScale+ MPSoC VCU TRD.  This TRD is made up of of several design modules.  A description of the design modules and links to the individual design module pages can be found in the Design Modules section below. 

Table of Contents

1 Revision History

This wiki page complements the 2019.2 a version of the MPSoC VCU TRD.

Change Log:

• Update all projects, IPs, and tools versions to 2019.2
• Added single-channel stream-based SCD and HDMI video support to the multistream audio design.
• Added multistream and DCI 4k resolution support to the PL DDR HDMI design.
• Added new LLP2 designs with HDMI interface supporting NV12, NV16 and XV20 formats for ultra-low-latency support.
• Added LLP2 design with the SDI interface supporting XV20 format for ultra-low-latency support.
• Added a design with SDI interface and plddr for supporting XV20 format and interlaced feature.
• Added support for PCIe-based file encoding and decoding.

2 Overview

This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of