Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PL DDR HLG SDI Video Capture and Display

Owned by Ronak Shah (Unlicensed)
Last updated: Jan 14, 2021 by Sunil Vaghela
21 min read

This page provides all the information related to VCU TRD PL DDR HLG SDI design.

This is a beta release and will be included in the future TRD releases as an additional design module. Also note that this page stands alone and does not rely on the common VCU TRD “Build and Run Flow” page.

Table of Contents

1 Overview

This module enables the capture of the High Dynamic Range(HLG) video from an SDI-Rx subsystem implemented in the PL. The High Dynamic Range(HLG) video can be displayed through the SDI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface. This module supports multi-stream for XV20 pixel format. In this design, PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60 FPS.

This module supports the Encoding-Decoding and Transmission of High Dynamic Range(HLG) video along with backward compatible Standard Dynamic Range(SDR) for SDI. It provides the ability to encode a wide dynamic range, while still being compatible with the existing transmission standards in the standard dynamic range (SDR) region. This HLG format encodes the HDR and SDR information in single signal enabling HDR-compatible TVs to display an enhanced image. Unlike HDR it does not have any metadata, rather it will use the ATC(Alternative transfer characteristics) SEI(supplemental enhanced information) information in the VUI(video usability information) to add extra encoding details.

From VCU point of view, there are two "types" of HLG, which you can enable:

  1. There is a HLG-SDR Backwards Compatible Mode, which uses the BT2020 value in the SPS VUI parameters instead of the HLG transfer characteristics. Then the VCU encoder will insert a 'Alternative Transfer Characteristics' (ATC) SEI with the HLG value. See below video frame snapshot captured in stream-eye:

Depending on version of stream-eye, you may not see SEI message correctly. But if you look at HEX viewer you will see ATC SEI in bit-stream.

0x93 - Payload Type (147 == ATC)
0x01 - Payload Size (1 byte)
0x12 - 18 (HLG EOTF value)
0x80 - payload bits ending

2. There is a HLG only mode. This directly uses the HLG value in the SPS VUI parameters. See below frame snapshot captured in stream-eye:

This design supports the following video interfaces:
Sources:

  • SDI-Rx capture pipeline implemented in the PL.

  • File source (SD card, USB storage, SATA hard disk).

  • Stream-In from network or internet.

Sinks:

  • SDI-Tx display pipeline implemented in the PL.

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 

    • AVC/HEVC encoding.

    • Encoder/decoder parameter configuration.

Streaming Interfaces:

  • 1G Ethernet PS GEM 

Video format:

  • XV20

Supported Resolution

The table below provides the supported resolution from GUI and command-line app in this design.

Resolution

Command Line

Single Stream

Multi Stream

4Kp60

√

X

4Kp30

√

X

1080p60

√

X

√ - Supported
x – Not supported

The below table gives information about the features supported in this design. 

Pipeline

Input Source

Format

Output Type

Resolution

Video Codec
Type

Pipeline

Input Source

Format

Output Type

Resolution

Video Codec
Type

Record/Stream-Out pipeline

SDI-Rx

XV20

File Sink/ Stream-Out

 4K/1080p

 HEVC/AVC

File/ Streaming Playback pipeline

File Source/ Stream-In

XV20

SDI-Tx

4K/1080p

HEVC/AVC

Serial pipeline

(Capture → Encode → Decode → Display)

 SDI-Rx

XV20

 SDI-Tx

 4K/1080p

 HEVC/AVC

RAW pipeline (capture->display)

 SDI-Rx

XV20

 SDI-Tx

 4K/1080p

N.A.

The below figure shows the HLG SDI Video Capture and HLG SDI Display design hardware block diagram.

The below figure shows the HLG SDI Video Capture and HLG SDI Display design software block diagram.

2 Hardware and Software Tools

2.1 Hardware Tools

Required :

  • ZCU106 evaluation board (rev C/D/E/F/1.0) with power cable

  • Class-10 SD card

  • Micro USB to USB-A cable for UART connection

  • Linux host machine to access zcu106

Optional :

  • USB pen drive formatted with the FAT32 file system and hub

  • SATA drive formatted with the FAT32 file system, external power supply, and data cable

2.2 Software Tools

Required :

Compatibility :

The VCU HLG SDI design has been tested successfully with the following components.

  • Phabrix Qx 12G Analyzer/Generator

    • Phabrix Qx is advanced tool for analysis and monitoring SDI standards - It also supports HLG. We have validated HLG serial and decode-display pipelines with Pharbix Qx Box, and analyzed the output HLG data.

  • SDI Receiver - AJA HA5-12G HDMI to 12G SDI converter

  • SDI Transmitter - AJA HI5-12G 12G SDI to HDMI converter

  • BNC to Micro BNC (HD-BNC) fiber cables to connect Converters and ZCU106 Board

    • The AJA HLG converters are good tools to converts normal SDR data to HLG data(HI5-12G), we have validated HLG record pipelines with use of AJA converters, and tested the recorded files with Phabrix Qx Box.

2.3 Download, Installation, and Licensing

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

  • UHD SDI GT - Included with Vivado - PG380

  • SDI-Rx/Tx Subsystem - Included with Vivado - PG289 & PG290

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

Hardware Evaluation keys allow you to simulate and implement your design, run timing analysis and generate a time-limited bitstream to program a Xilinx FPGA. The core in the programmed device will function in hardware for anywhere from 2 to 8 hours, depending on the core.

3 Board Setup

The below section will provide the information on the ZCU106 board setup for running TRD.

  1. Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.

  2. Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for specific design.

  3. Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.

  4. Connect 12V Power to the ZCU106 6-Pin Molex connector.

  5. Connect one end of SDI BNC cable to HD-BNC connector (SDI-Rx, J68) on board and another end to SDI source/HDMI source with HLG supported HDMI to SDI Converter.

  6. Connect one end of SDI BNC cable to HD-BNC connector (SDI-Tx, J10) on board and another end to SDI monitor/HDMI monitor with HLG supported SDI to HDMI Converter.

  7. For a USB storage device, connect the USB hub along with the mouse. (Optional)

  8. For SATA storage device, connect SATA data cable to SATA 3.0 port. (Optional).

  9. Set up a terminal session between a PC COM port and the serial port on the evaluation board (See the Determine which COM to use to access the USB serial port on the ZCU106 board for more details)

  10. Copy the HLG images into the SD card and insert the SD card on the board.

  11. The below images will show how to connect interfaces on the ZCU106 board.

The above figure shows all the ZCU106  board connections.

 The above figure shows all the ZCU106 board connector slots.

3.1 Determine which COM to use to access the USB serial port on the ZCU106 board

Make sure that the ZCU106 board is powered on and a micro USB cable is connected between the ZCU106 board and host PC. This ensures that the USB-to-serial bridge is enumerated by the PC host.

Open your computer's Control Panel by clicking on Start > Control Panel.

Note that the Start button is typically located in the lower-left corner of the screen. Occasionally, it is in the upper left corner.

  1. Click Device Manager to open the Device Manager window. Note: You may be asked to confirm opening the Device Manager. If so, click YES.

  2. Expand Ports (COM & LPT).

  3. Locate the Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 (COM#).

4. Note down the COM Port number for further steps.
5. Close the Device Manager by clicking the red X in the upper right corner of the window.

Launch any Terminal application like Tera term to view the serial messages

  1. Launch Tera Term and open the COM the port that is associated with Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 of the USB-to-serial bridge.

  2. Set the COM port to 115200 Baud rate, 8 bit data, none parity, 1 stop bit.

  3. Power ON the board which has an SD card. Switch ON SW1 to power the ZCU106 board.

  4. It boots Linux on board and It takes about a minute for Linux to boot. 

4 Download the TRD

5 Run Flow

The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME which is the home directory.

TRD package contents specific to VCU HLG SDI Video Capture and Display design are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_hlg_sdi to FAT32 formatted SD card directory.

rdf0616-zcu106-vcu-hlg-EA-2020-2 ├── apu │   └── vcu_petalinux_bsp ├── images │   └── vcu_hlg_sdi ├── pl │   ├── constrs │   ├── designs │   ├── prebuild │   ├── README.md │   └── srcs └── README.txt 9 directories, 2 files

TRD package contents specific to VCU HLG SDI Video Capture and Display design are placed in the following directory structure.

rdf0616-zcu106-vcu-hlg-EA-2020-2 ├── apu │   └── vcu_petalinux_bsp │   └── xilinx-vcu-zcu106-v2020.2-final.bsp ├── images │   └── vcu_hlg_sdi │   ├── autostart.sh │   ├── BOOT.BIN │   ├── boot.scr │   ├── config │   ├── image.ub │   ├── system.dtb │   └── vcu ├── pl │   ├── constrs │   ├── designs │   │   └── zcu106_HLG_SDI │   ├── prebuild │   │   └── zcu106_HLG_SDI │   ├── README.md │   └── srcs │   └── hdl └── README.txt 14 directories, 8 files

Configuration files (input.cfg) for various Resolutions are placed in the following directory structure in /media/card.

config ├── 1080p60 │ ├── Display │ ├── Record │ ├── Stream-in │ └── Stream-out ├── 4kp30 │ ├── Display │ ├── Record