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Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PL DDR HLG SDI Video Capture and Display

Zynq UltraScale+ MPSoC VCU TRD 2020.2 - PL DDR HLG SDI Video Capture and Display

Owned by Ronak Shah (Unlicensed)
Last updated: Jan 14, 2021 by Sunil Vaghela (Unlicensed)
21 min read

This page provides all the information related to VCU TRD PL DDR HLG SDI design.

This is a beta release and will be included in the future TRD releases as an additional design module. Also note that this page stands alone and does not rely on the common VCU TRD “Build and Run Flow” page.

Table of Contents

1 Overview

This module enables the capture of the High Dynamic Range(HLG) video from an SDI-Rx subsystem implemented in the PL. The High Dynamic Range(HLG) video can be displayed through the SDI-Tx subsystem implemented in the PL. The module can stream-out and stream-in live captured video frames through an Ethernet interface. This module supports multi-stream for XV20 pixel format. In this design, PL_DDR is used for decoding and PS_DDR for encoding so that DDR bandwidth would be enough to support high bandwidth VCU applications requiring simultaneous encoder and decoder operations and transcoding at 4k@60 FPS.

This module supports the Encoding-Decoding and Transmission of High Dynamic Range(HLG) video along with backward compatible Standard Dynamic Range(SDR) for SDI. It provides the ability to encode a wide dynamic range, while still being compatible with the existing transmission standards in the standard dynamic range (SDR) region. This HLG format encodes the HDR and SDR information in single signal enabling HDR-compatible TVs to display an enhanced image. Unlike HDR it does not have any metadata, rather it will use the ATC(Alternative transfer characteristics) SEI(supplemental enhanced information) information in the VUI(video usability information) to add extra encoding details.

From VCU point of view, there are two "types" of HLG, which you can enable:

  1. There is a HLG-SDR Backwards Compatible Mode, which uses the BT2020 value in the SPS VUI parameters instead of the HLG transfer characteristics. Then the VCU encoder will insert a 'Alternative Transfer Characteristics' (ATC) SEI with the HLG value. See below video frame snapshot captured in stream-eye:

Depending on version of stream-eye, you may not see SEI message correctly. But if you look at HEX viewer you will see ATC SEI in bit-stream.

0x93 - Payload Type (147 == ATC)
0x01 - Payload Size (1 byte)
0x12 - 18 (HLG EOTF value)
0x80 - payload bits ending

2. There is a HLG only mode. This directly uses the HLG value in the SPS VUI parameters. See below frame snapshot captured in stream-eye:

This design supports the following video interfaces:
Sources:

  • SDI-Rx capture pipeline implemented in the PL.

  • File source (SD card, USB storage, SATA hard disk).

  • Stream-In from network or internet.

Sinks:

  • SDI-Tx display pipeline implemented in the PL.

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 

    • AVC/HEVC encoding.

    • Encoder/decoder parameter configuration.

Streaming Interfaces:

  • 1G Ethernet PS GEM 

Video format:

  • XV20

Supported Resolution

The table below provides the supported resolution from GUI and command-line app in this design.

Resolution

Command Line

Single Stream

Multi Stream

4Kp60

√

X

4Kp30

√

X

1080p60

√

X

√ - Supported
x – Not supported

The below table gives information about the features supported in this design. 

Pipeline

Input Source

Format

Output Type

Resolution

Video Codec
Type

Pipeline

Input Source

Format

Output Type

Resolution

Video Codec
Type

Record/Stream-Out pipeline

SDI-Rx

XV20

File Sink/ Stream-Out

 4K/1080p

 HEVC/AVC

File/ Streaming Playback pipeline

File Source/ Stream-In

XV20

SDI-Tx

4K/1080p

HEVC/AVC

Serial pipeline

(Capture → Encode → Decode → Display)

 SDI-Rx

XV20

 SDI-Tx

 4K/1080p

 HEVC/AVC

RAW pipeline (capture->display)

 SDI-Rx

XV20

 SDI-Tx

 4K/1080p

N.A.

The below figure shows the HLG SDI Video Capture and HLG SDI Display design hardware block diagram.

The below figure shows the HLG SDI Video Capture and HLG SDI Display design software block diagram.

2 Hardware and Software Tools

2.1 Hardware Tools

Required :

  • ZCU106 evaluation board (rev C/D/E/F/1.0) with power cable

  • Class-10 SD card

  • Micro USB to USB-A cable for UART connection

  • Linux host machine to access zcu106

Optional :

  • USB pen drive formatted with the FAT32 file system and hub

  • SATA drive formatted with the FAT32 file system, external power supply, and data cable

2.2 Software Tools

Required :

Compatibility :

The VCU HLG SDI design has been tested successfully with the following components.

  • Phabrix Qx 12G Analyzer/Generator

    • Phabrix Qx is advanced tool for analysis and monitoring SDI standards - It also supports HLG. We have validated HLG serial and decode-display pipelines with Pharbix Qx Box, and analyzed the output HLG data.

  • SDI Receiver - AJA HA5-12G HDMI to 12G SDI converter

  • SDI Transmitter - AJA HI5-12G 12G SDI to HDMI converter

  • BNC to Micro BNC (HD-BNC) fiber cables to connect Converters and ZCU106 Board

    • The AJA HLG converters are good tools to converts normal SDR data to HLG data(HI5-12G), we have validated HLG record pipelines with use of AJA converters, and tested the recorded files with Phabrix Qx Box.

2.3 Download, Installation, and Licensing

The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which include the Vivado Integrated Design Environment (IDE), High-Level Synthesis tool, and System Generator for DSP. This guide also provides information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.

LogiCORE IP Licensing

The following IP cores require a license to build the design.

  • UHD SDI GT - Included with Vivado - PG380

  • SDI-Rx/Tx Subsystem - Included with Vivado - PG289 & PG290

To obtain the LogiCORE IP license, please visit the respective IP product page and get the license.

Hardware Evaluation keys allow you to simulate and implement your design, run timing analysis and generate a time-limited bitstream to program a Xilinx FPGA. The core in the programmed device will function in hardware for anywhere from 2 to 8 hours, depending on the core.

3 Board Setup

The below section will provide the information on the ZCU106 board setup for running TRD.

  1. Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.

  2. Insert the SD card with the images copied into the SD card slot J100. Please find here how to prepare the SD card for specific design.

  3. Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.

  4. Connect 12V Power to the ZCU106 6-Pin Molex connector.

  5. Connect one end of SDI BNC cable to HD-BNC connector (SDI-Rx, J68) on board and another end to SDI source/HDMI source with HLG supported HDMI to SDI Converter.

  6. Connect one end of SDI BNC cable to HD-BNC connector (SDI-Tx, J10) on board and another end to SDI monitor/HDMI monitor with HLG supported SDI to HDMI Converter.

  7. For a USB storage device, connect the USB hub along with the mouse. (Optional)

  8. For SATA storage device, connect SATA data cable to SATA 3.0 port. (Optional).

  9. Set up a terminal session between a PC COM port and the serial port on the evaluation board (See the Determine which COM to use to access the USB serial port on the ZCU106 board for more details)

  10. Copy the HLG images into the SD card and insert the SD card on the board.

  11. The below images will show how to connect interfaces on the ZCU106 board.

The above figure shows all the ZCU106  board connections.

 The above figure shows all the ZCU106 board connector slots.

3.1 Determine which COM to use to access the USB serial port on the ZCU106 board

Make sure that the ZCU106 board is powered on and a micro USB cable is connected between the ZCU106 board and host PC. This ensures that the USB-to-serial bridge is enumerated by the PC host.

Open your computer's Control Panel by clicking on Start > Control Panel.

Note that the Start button is typically located in the lower-left corner of the screen. Occasionally, it is in the upper left corner.

  1. Click Device Manager to open the Device Manager window. Note: You may be asked to confirm opening the Device Manager. If so, click YES.

  2. Expand Ports (COM & LPT).

  3. Locate the Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 (COM#).

4. Note down the COM Port number for further steps.
5. Close the Device Manager by clicking the red X in the upper right corner of the window.

Launch any Terminal application like Tera term to view the serial messages

  1. Launch Tera Term and open the COM the port that is associated with Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 of the USB-to-serial bridge.

  2. Set the COM port to 115200 Baud rate, 8 bit data, none parity, 1 stop bit.

  3. Power ON the board which has an SD card. Switch ON SW1 to power the ZCU106 board.

  4. It boots Linux on board and It takes about a minute for Linux to boot. 

4 Download the TRD

5 Run Flow

The TRD package is released with the source code, Vivado project, Petalinux BSP, and SD card image that enables the user to run the demonstration. It also includes the binaries necessary to configure and boot the ZCU106 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as TRD_HOME which is the home directory.

TRD package contents specific to VCU HLG SDI Video Capture and Display design are placed in the following directory structure. The user needs to copy all the files from the $TRD_HOME/images/vcu_hlg_sdi to FAT32 formatted SD card directory.

rdf0616-zcu106-vcu-hlg-EA-2020-2 ├── apu │   └── vcu_petalinux_bsp ├── images │   └── vcu_hlg_sdi ├── pl │   ├── constrs │   ├── designs │   ├── prebuild │   ├── README.md │   └── srcs └── README.txt 9 directories, 2 files

TRD package contents specific to VCU HLG SDI Video Capture and Display design are placed in the following directory structure.

rdf0616-zcu106-vcu-hlg-EA-2020-2 ├── apu │   └── vcu_petalinux_bsp │   └── xilinx-vcu-zcu106-v2020.2-final.bsp ├── images │   └── vcu_hlg_sdi │   ├── autostart.sh │   ├── BOOT.BIN │   ├── boot.scr │   ├── config │   ├── image.ub │   ├── system.dtb │   └── vcu ├── pl │   ├── constrs │   ├── designs │   │   └── zcu106_HLG_SDI │   ├── prebuild │   │   └── zcu106_HLG_SDI │   ├── README.md │   └── srcs │   └── hdl └── README.txt 14 directories, 8 files

Configuration files (input.cfg) for various Resolutions are placed in the following directory structure in /media/card.

config ├── 1080p60 │ ├── Display │ ├── Record │ ├── Stream-in │ └── Stream-out ├── 4kp30 │ ├── Display │ ├── Record │ ├── Stream-in │ └── Stream-out └── 4kp60 │ ├── Display │ ├── Record │ ├── Stream-in │ └── Stream-out └── input.cfg 15 directories, 1 file

5.1 Prepare a SD-Card

  • The user needs to copy all the files from the $TRD_HOME/images/vcu_hlg_sdi/ to FAT32 formatted SD card directory.

  • Power on the board; make sure INIT_B, DONE and all power rail LEDs are lit green

  • After a successful boot, a shell prompt would appear as shown below.

root@zcu106_vcu_hlg_sdi:~#

  • The SD card file system is mounted at /media/card. Optional storage medium SATA and USB are mounted at /media/sata and /media/usb respectively.

5.2 GStreamer Application (vcu_gst_app)

The vcu_gst_app is a command-line multi-threaded Linux application. The command-line application requires an input configuration file (input.cfg) to be provided in the plain text.

Execution of the application is shown below:

$ vcu_gst_app <path to *.cfg file>

Example:

4kp60 HEVC_HIGH Display Pipeline execution

$ vcu_gst_app /media/card/config/4kp60/Display/Single_4kp60_HEVC_HIGH.cfg

4kp60 HEVC_HIGH Record Pipeline execution

$ vcu_gst_app /media/card/config/4kp60/Record/Single_4kp60_HEVC_HIGH.cfg

4kp60 HEVC_HIGH Stream-out Pipeline execution

$ vcu_gst_app /media/card/config/4kp60/Stream-out/Single_4kp60_HEVC_HIGH.cfg

4kp60 HEVC_HIGH Stream-in Pipeline execution

$ vcu_gst_app /media/card/config/4kp60/Stream-in/input.cfg

Make sure SDI-Rx should be configured to 4kp60 mode.

To measure the latency of the pipeline, run the below command. The latency data is huge, so dump it to a file.

$ GST_DEBUG="GST_TRACER:7" GST_TRACERS="latency" GST_DEBUG_FILE=/run/latency.log vcu_gst_app /media/card/config/4kp60/Display/Single_4kp60_HEVC_HIGH.cfg

5.3 QoS Configuration

Check the Read QoS, Write QoS, Read Commands Issuing Capability and Write Commands Issuing Capability configuration of HP ports that interface VCU with PS DDR.

For VCU traffic, the QoS should be set as Best Effort (BE) and outstanding transaction count for read/write commands should be set to maximum i.e. 0xF for all AXI HP ports.

The AXI-QoS{3:0] lines behavior define three types of following Traffic in Decimal format on the AXI Bus.

Traffic Class

Read QoS Value (default)

Write QoS Value (default)

Best Effort (BE)

0-3

0-7

Video (V)

4-11

8-15

Low Latency (LL)

12-15

N/A

 Below is the reference QoS configuration script as per VCU recommendation.

#!/bin/bash /sbin/devmem 0xfd360008 w 0x3 #RDQoS for S_AXI_HPC0_FPD /sbin/devmem 0xfd370008 w 0x3 #RDQoS for S_AXI_HPC1_FPD /sbin/devmem 0xfd380008 w 0x3 #RDQoS for S_AXI_HP0_FPD /sbin/devmem 0xfd390008 w 0x3 #RDQoS for S_AXI_HP1_FPD /sbin/devmem 0xfd3a0008 w 0x3 #RDQoS for S_AXI_HP2_FPD /sbin/devmem 0xfd3b0008 w 0x3 #RDQoS for S_AXI_HP3_FPD /sbin/devmem 0xfd36001c w 0x3 #WRQoS for S_AXI_HPC0_FPD /sbin/devmem 0xfd37001c w 0x3 #WRQoS for S_AXI_HPC1_FPD /sbin/devmem 0xfd38001c w 0x3 #WRQoS for S_AXI_HP0_FPD /sbin/devmem 0xfd39001c w 0x3 #WRQoS for S_AXI_HP1_FPD /sbin/devmem 0xfd3a001c w 0x3 #WRQoS for S_AXI_HP2_FPD /sbin/devmem 0xfd3b001c w 0x3 #WRQoS for S_AXI_HP3_FPD /sbin/devmem 0xfd360004 w 0xF #RDISSUE for S_AXI_HPC0_FPD /sbin/devmem 0xfd370004 w 0xF #RDISSUE for S_AXI_HPC1_FPD /sbin/devmem 0xfd380004 w 0xF #RDISSUE for S_AXI_HP0_FPD /sbin/devmem 0xfd390004 w 0xF #RDISSUE for S_AXI_HP1_FPD /sbin/devmem 0xfd3A0004 w 0xF #RDISSUE for S_AXI_HP2_FPD /sbin/devmem 0xfd3B0004 w 0xF #RDISSUE for S_AXI_HP3_FPD /sbin/devmem 0xfd360018 w 0xF #WRISSUE for S_AXI_HPC0_FPD /sbin/devmem 0xfd370018 w 0xF #WRISSUE for S_AXI_HPC1_FPD /sbin/devmem 0xfd380018 w 0xF #WRISSUE for S_AXI_HP0_FPD /sbin/devmem 0xfd390018 w 0xF #WRISSUE for S_AXI_HP1_FPD /sbin/devmem 0xfd3A0018 w 0xF #WRISSUE for S_AXI_HP2_FPD /sbin/devmem 0xfd3B0018 w 0xF #WRISSUE for S_AXI_HP3_FPD

6 Build Flow

The following tutorials assume that the $TRD_HOME environment variable is set as given below.

$ export TRD_HOME=</path/to/downloaded/zipfile>/rdf0616-zcu106-vcu-hlg-EA-2020-2

6.1 Hardware Design

$ vivado -source designs/zcu106_HLG_SDI/project.tcl

After executing the script, the Vivado IPI block design comes up as shown in the below figure.

 

  • Click on “Generate Bitstream”.

If the user gets any pop-up with “No implementation Results available”. Click “Yes”. Then, if any pop-up comes up with “Launch runs”, Click "OK”.

The design is implemented and a pop-up window comes up saying “Open Implemented Design”. Click "OK".

After opening the implemented design, the window looks as shown in the below figure.

The actual results might graphically look different than the image shown

The project.tcl has scripts to Export Hardware and generate the .xsa file.
Go to File > Export > Export Hardware

In the Export Hardware Platform window click Next.

 

In the next window, select Include bitstream and click Next.

The default XSA file name is <hardware design name_wrapper>. Choose the path where the XSA file has to be written.

By default, the XSA is created at $TRD_HOME/pl/build/<hardware design name>/<hardware design name.sdk>/<hardware design name_wrapper.xsa>.

As an e.g  the XSA is created at $TRD_HOME/pl/build/zcu106_trd/zcu106_trd.sdk/zcu106_HLG_SDI_wrapper.xsa for VCU TRD hardware design .

Click Finish for the XSA file to be generated.

6.2 VCU PetaLinux BSP

This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
PetaLinux Installation: Refer to the PetaLinux Tools Documentation UG1144 for installation.
Kernel and DT Documentation: Refer to the AR #75894 for Device Tree changes and Kernel patches required for ZCU106 VCU HLG BSP.

It is recommended to follow the build steps in sequence.

$ source <path/to/petalinux-installer>/tool/petalinux-v2020.2-final/settings.sh $ echo $PETALINUX

Post PetaLinux installation $PETALINUX environment variable should be set

  • Create a PetaLinux project.

$ cd $TRD_HOME/apu/vcu_petalinux_bsp $ petalinux-create -t project -s xilinx-vcu-zcu106-v2020.2-final.bsp

  • Configure the PetaLinux project.

$ cd xilinx-vcu-zcu106-v2020.2-final $ petalinux-config --get-hw-description=$TRD_HOME/pl/prebuild/zcu106_HLG_SDI/

Please note that, below config options are disabled in xilinx-vcu-zcu106-v2020.2-final/project-spec/configs/config for VCU HLG BSP

  • CONFIG_SUBSYSTEM_FPGA_MANAGER : It adds overlay dtb nodes, and overlay dtb nodes are not used in VCU HLG; so it is disabled

  • CONFIG_SUBSYSTEM_REMOVE_PL_DTB : PL IPs are used in VCU HLG design, so keep it disabled to generate PL DTB nodes

  • If the Vivado project is modified, the user is expected to configure the bsp with the modified .xsa file and build. e.g.

$ petalinux-config --get-hw-description=$TRD_HOME/pl/build/zcu106_HLG_SDI/

  • Create a soft link of design dtsi file to system-user.dtsi using below command

$ cd project-spec/meta-user/recipes-bsp/device-tree/files/ $ ln -sf vcu_plddr_sdi.dtsi system-user.dtsi $ cd ../../../../../

  • Build the PetaLinux project

$ petalinux-build

  • Build SDK components to use it as sysroot for application development.

$ petalinux-build --sdk $ petalinux-package --sysroot

  • Create a boot image (BOOT.BIN) including FSBL, ATF, bitstream, and u-boot.

$ cd images/linux $ petalinux-package --boot --fsbl zynqmp_fsbl.elf --u-boot u-boot.elf --pmufw pmufw.elf --fpga system.bit

  • Copy the generated boot image and Linux image to the SD card directory.

$ cp BOOT.BIN image.ub boot.scr $TRD_HOME/images/vcu_hlg_sdi/

6.3 VCU GST APP

vcu_gst_app and supporting library will be built as a vcu-gst-app recipe inside petalinux-project. Refer project-spec/meta-user/recipes-apps/vcu-gst-app directory inside petalinux project for vcu-gst-app recipe. Source of vcu_apm_lib, vcu_video_lib, vcu_gst_lib and vcu_gst_app is provided as zip inside project-spec/meta-user/recipes-apps/vcu-gst-app/files/ directory. vcu_gst_app will be built as part of petalinux project and the executable is placed in /usr/bin location of rootfs. User can update the zip file if any source code modifications need to be and run following command to build vcu-gst-app recipe.

$ petalinux-build -c vcu-gst-app

7 Other Information

7.1 Known Issues

7.2 Limitations

8 Appendix A - Input Configuration File (input.cfg)

The example configuration files are stored at /media/card/config/ folder.

Configuration Type

Configuration Name

Description

Available Options

Configuration Type

Configuration Name

Description

Available Options

Common

 

Common Configuration

It is the starting point of common configuration

 

Num of Input

Number of input

1

Output

Select the video interface.

SDI

Out Type

Type of output

display, record, stream

Display Rate

Pipeline frame rate

30, 60

Exit

It indicates to the application that the configuration is over

 

 

Input

Input Configuration

It is the starting point of the input configuration

 

Input Num

Starting Nth input configuration

1

Input Type

Input source type

SDI, File, Stream

Uri

File path or Network URL. Applicable for file playback and Stream-in pipeline only. Supported file formats for playback are ts, mp4, and mkv.

file:///media/usb/abc.ts (for file path), udp://192.168.25.89:5004/ (for Network streaming, Here 192.168.25.89 is IP address and 5004 is port number)

Raw

To tell the pipeline is processed or pass-through

TRUE, FALSE

Width

The width of the live source

3840,1920

Height

The height of the live source

2160, 1080

Format

The format of input data

XV20

Exit

It indicates to the application that the configuration is over

 

Encoder

 

Encoder Configuration

It is the starting point of encoder configuration

 

Encoder Num

Starting Nth encoder configuration

1

Encoder Name

Name of the encoder

AVC, HEVC

Profile

Name of the profile

baseline, main or high for AVC. Main for HEVC.

Rate Control

Rate control options

CBR, VBR, and low-latency.

Filler Data

Filler Data NAL units for CBR rate control

True, False

QP

QP control mode used by the VCU encoder

Uniform, Auto

L2 Cache

Enable or Disable L2Cache buffer in encoding process.

True, False

Latency Mode

Encoder latency mode.

normal, sub_frame

Low Bandwidth

If enabled, decrease the vertical search range used for P-frame motion estimation to reduce the bandwidth.

True, False

Gop Mode

Group of Pictures mode.

Basic, low_delay_p, low_delay_b

Bitrate

Target bitrate in Kbps

1-60000

B Frames

Number of B-frames between two consecutive P-frames

0-4

Slice

The number of slices produced for each frame. Each slice contains one or more complete macroblock/CTU row(s). Slices are distributed over the frame as regularly as possible. If slice-size is defined as well more slices may be produced to fit the slice-size requirement

4 to 22 : 4Kp resolution with HEVC codec
4 to 32 : 4Kp resolution with AVC codec
4 to 32 : 1080p resolution with HEVC codec
4 to 32 : 1080p resolution with AVC codec

GoP Length

The distance between two consecutive I frames

1-1000

GDR Mode

It specifies which Gradual Decoder Refresh(GDR) scheme should be used when gop-mode = low_delay_p

GDR mode is currently supported with LLP1/LLP2 low-delay-p use-cases only

Horizontal/Vertical/Disabled

Entropy Mode

It specifies the entropy mode for H.264 (AVC) encoding process

CAVLC/CABAC/Default

Max Picture Size

It is used to curtail instantaneous peak in the bit-stream using this parameter. It works in CBR/VBR rate-control only. When it is enabled, max-picture-size value is calculated and set with 10% of AllowedPeakMargin. i.e. max-picture-size =  (TargetBitrate / FrameRate) * 1.1

TRUE/FALSE

HLG_SDR_Compatible

It specifies the whether vcu will use the HLG Only mode or Backward-Compatible-Mode.

By default, vcu-gst-app will use HLG Only mode.

TRUE/FALSE

Preset

Encoder configuration Preset

HEVC_HIGH, HEVC_MEDIUM, HEVC_LOW, AVC_HIGH, AVC_MEDIUM, AVC_LOW, Custom

Exit

It indicates to the application that the configuration is over

 

Record

Record Configuration

It is the starting point of record configuration.

 

Record Num

Starting Nth record configuration.

1

Out File Name

Record file path.

e.g. /media/usb/abc.ts

Duration

Duration in minutes.

1-3

Exit

It indicates to the application that the configuration is over.

 

Streaming

Streaming Configuration

It is the starting point of streaming configuration.

 

Streaming Num

Starting Nth Streaming configuration

1

Host IP

The host to send the packets to

192.168.25.89 or Windows PC IP

Port:

The port to send the packets to.

5004

Exit

It indicates to the application that the configuration is over.

 

Trace

Trace Configuration

It is the starting point of trace configuration.

 

FPS Info

To display fps info on the console.

True, False

APM Info

To display APM counter number on the console.

True, False

Pipeline Info

To display pipeline info on console.

True, False

Exit

It indicates to the application that the configuration is over.

 

9 Appendix B - SDI-Rx/Tx Link-up and GStreamer Commands

This section covers configuration of SDI-Rx using media-ctl utility and SDI-Tx using modetest utility, along with demonstrating SDI-Rx/Tx link-up issue and steps to switch resolution. It also contains sample GStreamer SDI XV20 pipelines for Display, Record, Stream-In and Stream-Out use-cases.

Run the below command to check the SDI link status, resolution, video node and output format of the SDI input source. Run the below command for all media nodes to print media device topology where media0 represents different media nodes. In the topology, log look for the v_smpte_uhdsdi_rx_ss string to identify the SDI input source media node. The media-ctl command generated as part of petalinux bsp will support all the vcu supported formats like NV12, NV16, XV15 and XV20.

$ media-ctl -p -d /dev/media0

Check resolution and frame-rate of of dv.detect under v_smpte_uhdsdi_rx_ss node.

  • When HLG SDI source is connected to 4Kp60 resolution, it shows as below:

root@zcu106_vcu_hlg_sdi:/media/card# media-ctl -p -d /dev/media0 -----> media node for SDI input source Media controller API version 5.4.0 Media device information ------------------------ driver xilinx-video model Xilinx Video Composite Device serial bus info hw revision 0x0 driver version 5.4.0 Device topology - entity 1: vcap_sdirxsdi_rx_input_v_smpte_ (1 pad, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 -----> Video node for SDI input source pad0: Sink <- "a0030000.v_smpte_uhdsdi_rx_ss":0 [ENABLED] - entity 5: a0030000.v_smpte_uhdsdi_rx_ss (1 pad, 1 link) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Source [fmt:UYVY10_1X20/3840x2160@1000/60000 field:none colorspace:bt2020 xfer:unknown ycbcr:bt2020 quantization:lim-range] [dv.detect:BT.656/1120 3840x2160p60 (4400x2250) stds:CEA-861 flags:can-reduce-fps,CE-video,has-cea861-vic] ---> SDI-Rx link up -> "vcap_sdirxsdi_rx_input_v_smpte_":0 [ENABLED]

xfer function is 'unknown' because upstream kernel does not support HLG enumeration. This will no affect functionality. This needs to be added by upstream and media-ctl application.

  • When the SDI source is not connected, it shows:

root@zcu106_vcu_hlg_sdi:/media/card# media-ctl -p -d /dev/media0 -----> media node for SDI input source Media controller API version 5.4.0 Media device information ------------------------ driver xilinx-video model Xilinx Video Composite Device serial bus info hw revision 0x0 driver version 5.4.0 Device topology - entity 1: vcap_sdirxsdi_rx_input_v_smpte_ (1 pad, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 -----> Video node for SDI input source pad0: Sink <- "a0030000.v_smpte_uhdsdi_rx_ss":0 [ENABLED] - entity 5: a0030000.v_smpte_uhdsdi_rx_ss (1 pad, 1 link) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Source [dv.query:no-lock] -----> link is not detected -> "vcap_sdirxsdi_rx_input_v_smpte_":0 [ENABLED]

Here dv.query:no-lock under v_smpte_uhdsdi_rx_ss node shows SDI-Rx source is not connected or SDI-Rx source is not active (Try waking up the device by pressing a key on remote).

Modetest commands:

  • Modetest command for 4Kp60 Display

$ modetest -M xlnx -s 35:3840x2160-60@XV20 -w 35:sdi_mode:5 -w 35:sdi_data_stream:8 -w 35:is_frac:0 -w 35:c_encoding=1

  • Modetest command for 4Kp30 Display

$ modetest -M xlnx -s 35:3840x2160-30@XV20 -w 35:sdi_mode:4 -w 35:sdi_data_stream:8 -w 35:is_frac:0 -w 35:c_encoding=1

  • Modetest command for 1080p60 Display

$ modetest -M xlnx -s 35:1920x1080-60@XV20 -w 35:sdi_mode:2 -w 35:sdi_data_stream:2 -w 35:is_frac:0 -w 35:c_encoding=1

  • Follow the below steps to switch the SDI-Rx resolution from 1080p60 to 4Kp60.

    • Check current SDI Input Source Resolution (1080p60) by following the above-mentioned steps.

    • Run vcu_gst_app for current SDI resolution (1080p60) by executing the following command.

$ vcu_gst_app /media/card/config/input.cfg

Below configurations needs to be set in input.cfg for SDI-1080p60.

Common Configuration : START Num Of Input : 1 Output : SDI Out Type : Display Frame Rate : 60 Exit Input Configuration : START Input Num : 1 Input Type : SDI Raw : TRUE Width : 1920 Height : 1080 Format : XV20 Exit

  • Change Resolution of SDI Input Source from 1080p60 to 4Kp60 by following the below steps.

    • Set the SDI source resolution to 4Kp60 (Home page → settings → display & Sound → Resolution → change to 4Kp60).

    • Save the configuration to take place the change.

    • Verify desired SDI Input Source Resolution (4Kp60) by following the above-mentioned steps.

  • The table below lists the parameters of the pixel format.

After booting you need to run the modetest command(mandatory) for respective resolution you want to validate.

Pixel Format

GStreamer Format

Media Bus Format

GStreamer HEVC Profile

GStreamer AVC Profile

Kmssink Plane-id

Pixel Format

GStreamer Format

Media Bus Format

GStreamer HEVC Profile

GStreamer AVC Profile

Kmssink Plane-id

XV20

NV16_10LE32

UYVY10_1X20

main-422-10

high-4:2:2

32

  • All HLG GStreamer pipelines are only validated with Phabrix Qx 12G SDI Analyzer/Generator. It is a possibility that, HLG behavior might be different with actual setup containing HLG media source and display.

  • In record use-case, file location should be USB-3.0/SATA/RAMdisk to avoid the read-write bandwidth issue.

  • Video0 in the each below gst-launch pipelines indicates a video node for the input source.

  • Run the following gst-launch-1.0 command to display raw HLG SDI video using the GStreamer pipeline.

$ gst-launch-1.0 v4l2src device=/dev/video0 io-mode=4 ! video/x-raw, format=NV16_10LE32, width=3840, height=2160, framerate=60/1 ! queue max-size-bytes=-1 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

  • Run the following gst-launch-1.0 command to display processed(capture → encode → decode → display) HLG Only SDI video using the GStreamer pipeline.

$ gst-launch-1.0 -v v4l2src device=/dev/video0 io-mode=4 ! video/x-raw, width=3840, height=2160, framerate=60/1, format=NV16_10LE32 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 ! video/x-h265, alignment=au ! queue max-size-bytes=0 ! omxh265dec ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

  • Run the following gst-launch-1.0 command to display processed(capture → encode → decode → display) HLG-SDR-Compatible SDI video using the GStreamer pipeline.

$ gst-launch-1.0 -v v4l2src device=/dev/video0 io-mode=4 ! video/x-raw, width=3840, height=2160, framerate=60/1, format=NV16_10LE32 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 hlg-sdr-compatible=TRUE ! video/x-h265, alignment=au ! queue max-size-bytes=0 ! omxh265dec ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

  • Run the following gst-launch-1.0 command to record HLG Only SDI video using the GStreamer pipeline.

$ gst-launch-1.0 v4l2src device=/dev/video0 io-mode=4 num-buffers=3600 ! video/x-raw, width=3840, height=2160, format=NV16_10LE32, framerate=60/1 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 ! video/x-h265, alignment=au ! mpegtsmux alignment=7 name=mux ! filesink location="/run/test.ts"

  • Run the following gst-launch-1.0 command to record HLG-SDR-Compatible SDI video using the GStreamer pipeline.

$ gst-launch-1.0 v4l2src device=/dev/video0 io-mode=4 num-buffers=3600 ! video/x-raw, width=3840, height=2160, format=NV16_10LE32, framerate=60/1 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 hlg-sdr-compatible=TRUE ! video/x-h265, alignment=au ! mpegtsmux alignment=7 name=mux ! filesink location="/run/test.ts"

  • Run the following gst-launch-1.0 command to play the recorded HLG Only / HLG-SDR-Compatible video file using the GStreamer pipeline.

$ gst-launch-1.0 uridecodebin uri="file:///run/test.ts" name=decode ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

  • Run the following gst-launch-1.0 command to capture, encode and stream-out HLG Only SDI video using the GStreamer pipeline, where 192.168.25.89 is host/client IP address and 5004 is port number.

$ gst-launch-1.0 v4l2src device=/dev/video0 io-mode=4 ! video/x-raw, width=3840, height=2160, format=NV16_10LE32, framerate=60/1 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 periodicity-idr=60 ! video/x-h265, alignment=au ! h265parse ! queue ! mpegtsmux alignment=7 name=mux ! rtpmp2tpay ! udpsink host=192.168.25.89 port=5004 buffer-size=60000000 max-bitrate=120000000 max-lateness=-1 qos-dscp=60 async=false

  • Run the following gst-launch-1.0 command to stream-in, decode and play HLG-Only SDI video using the GStreamer pipeline, where 5004 is port number.

$ gst-launch-1.0 udpsrc port=5004 buffer-size=60000000 caps="application/x-rtp, clock-rate=90000" ! rtpjitterbuffer latency=1000 ! rtpmp2tdepay ! tsparse ! video/mpegts ! tsdemux name=demux ! queue ! h265parse ! video/x-h265, alignment=au ! omxh265dec ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

  • Run the following gst-launch-1.0 command to capture, encode and stream-out HLG-SDR-Compatible SDI video using the GStreamer pipeline, where 192.168.25.89 is host/client IP address and 5004 is port number.

$ gst-launch-1.0 v4l2src device=/dev/video0 io-mode=4 ! video/x-raw, width=3840, height=2160, format=NV16_10LE32, framerate=60/1 ! omxh265enc qp-mode=auto gop-mode=basic gop-length=60 b-frames=0 target-bitrate=60000 num-slices=8 control-rate=constant prefetch-buffer=true low-bandwidth=false filler-data=true cpb-size=1000 initial-delay=500 periodicity-idr=60 hlg-sdr-compatible=TRUE ! video/x-h265, alignment=au ! h265parse ! queue ! mpegtsmux alignment=7 name=mux ! rtpmp2tpay ! udpsink host=192.168.25.89 port=5004 buffer-size=60000000 max-bitrate=120000000 max-lateness=-1 qos-dscp=60 async=false

  • Run the following gst-launch-1.0 command to stream-in, decode and play HLG-SDR-Compatible SDI video using the GStreamer pipeline, where 5004 is port number.

$ gst-launch-1.0 udpsrc port=5004 buffer-size=60000000 caps="application/x-rtp, clock-rate=90000" ! rtpjitterbuffer latency=1000 ! rtpmp2tdepay ! tsparse ! video/mpegts ! tsdemux name=demux ! queue ! h265parse ! video/x-h265, alignment=au ! omxh265dec ! queue max-size-bytes=0 ! fpsdisplaysink name=fpssink text-overlay=false 'video-sink=kmssink driver-name=xlnx connector-properties="props,sdi_mode=5,sdi_data_stream=8,is_frac=0,c_encoding=1" show-preroll-frame=false hold-extra-sample=true async=false sync=false' -v

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