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Zynq UltraScale＋ MPSoC VCU TRD 2019.1 - HDMI Video Capture

Zynq UltraScale＋ MPSoC VCU TRD 2019.1 - HDMI Video Capture

Owned by Saket Kumar Bafna (Unlicensed)
Last updated: Jun 06, 2019 by Maulik K Patel (Unlicensed)

Zynq UltraScale＋ MPSoC VCU TRD 2019.1 - HDMI Video Capture


Table of Contents


1 Overview

The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks. 

This design supports the following video interfaces:

Sources:

  • HDMI-Rx capture pipeline implemented in the PL.

Sink:

  • Stream-out from network or internet.
  • File sink (SD card, USB storage, SATA hard disk).

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 
    • AVC/HEVC encoding.
    • Encoder/decoder parameter configuration.

Streaming Interfaces:

  • 1G Ethernet PS GEM 

Video Format:

  • NV12


Supported Resolution:

The table below provides the supported resolution from GUI and command line app in this design.

Resolution
GUICommand Line
Single StreamSingle Stream
4kp60X√
4kp30X√
1080p60X√

√ - Supported
NA – Not applicable
x – Not supported

The below table gives information about the features supported in this design. 

Pipeline

Input source

Output Type

Resolution

VCU codec

Single Stream: Record/Stream-Out pipeline

HDMI-Rx

File Sink/ Stream-Out

4K/1080p

HEVC/AVC

The below figure shows the HDMI Video Capture design hardware block diagram.


The below figure shows the HDMI Video Capture design software block diagram.


1.1 Board Setup

Refer below link for Board Setup