Zynq UltraScale+ MPSoC VCU TRD 2020.2

This page provides an overview of the 2020.2 version of the Zynq UltraScale+ MPSoC VCU TRD.  This TRD is made up of several design modules.  A description of the design modules and links to the individual design module pages can be found in the Design Modules below.

This page complements the TRD User Guide: UG1250

Table of Contents

1 Revision History

Change Log:

  • Updated all projects, IPs, and tools versions to 2020.2

  • Updated Vivado HLS IPs to Vitis HLS IPs in all designs

  • Updated PL DDR HDMI design with single-stream HDR10 support

  • Updated PL DDR SDI design with initial 8 channel Audio support

  • Added support for Quad Sensor MIPI CSI design using Avnet Quad Camera FMC module

  • Added support for different XAVC standards compliance profiles

  • Added AXI4-Stream Broadcaster driver instead of dummy driver for multi-stream HDMI use-cases


2 Overview

This is the main page of VCU TRD wiki, which has links to redirect wiki pages corresponding to individual design modules. It also explains the complete feature list and the supported resources of all the designs. TRD package web link is provided for the user to download. This page also gives information on required software tools, IP licenses.

The Zynq® UltraScale+™ MPSoC Video Codec Unit (VCU) Targeted Reference Design (TRD) consists of an embedded video encoding/decoding application that runs on the Processing System (PS). The overall functionality of the TRD is partitioned between the Processing System (PS), Video Codec Unit, and Programmable Logic (PL) for optimal performance. 

The primary goal of this TRD is to demonstrate the capabilities of the VCU core which is an integrated hard block present in Zynq UltraScale+ MPSoC EV devices. The TRD serves as a platform for the user to tune the performance parameters of VCU and arrives at an optimal configuration for encoder and decoder blocks for their specific use case. The TRD uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.

2.1 TRD Support

The TRD supports the following video interfaces.

Sources up-to 4K(3840 x 2160/4096 x 2160)-60FPS:

  • Test pattern generator (TPG) implemented in the PL.

  • HDMI-Rx capture pipeline implemented in the PL.

  • MIPI CSI-2 Rx capture pipeline implemented in the PL.

  • File source (SD card, USB storage, SATA hard disk).

  • Stream-In from network or internet.

  • SDI-Rx capture pipeline implemented in the PL.

Sinks up-to 4K(3840 x 2160/4096 x 2160)-60FPS for HDMI/SDI and 4K-30FPS for Display Port

  • DP Tx display pipeline in the PS.

  • HDMI-Tx display pipeline implemented in the PL.

  • SDI-Tx display pipeline implemented in the PL.

VCU Codec

  • Video Encode/Decode capability using VCU hard block in PL 

    • H.264/H.265 encoding

    • Encoder/decoder parameter configuration using OMX interface

    • Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput

Audio Codec

  • Opus 2 channel 48KHz 

Streaming Interfaces

  • 1G Ethernet PS GEM 

  • 10G PL Ethernet

Serial Communication

  • PCIe(Peripheral Component Interconnect Express)

Video format

  • NV12

  • NV16

  • XV15

  • XV20

The below figure shows the TRD block diagram. It consists of all the Design Modules. The components of each design module are highlighted in unique colors in the diagram. The remaining blocks are common to all design modules as shown.

2.2 Design Modules

The VCU TRD 2020.2 version consists of Eleven design-modules as described below. Individual links below will redirect to the corresponding wiki pages and build and run the flow of individual designs modules. 

Design Module #

Project Name

TRD Pre-built images
(rdf0428-zcu106-vcu-trd-2020-2/images)

Description

Design Module #

Project Name

TRD Pre-built images
(rdf0428-zcu106-vcu-trd-2020-2/images)

Description

1

VCU TRD Multi Stream Video Capture and Display

vcu_multistream_nv12

Multi-stream design supporting HDMI-Rx, TPG, MIPI, HDMI-Tx, DP along with showcasing capabilities of VCU

2

PL DDR SDI Audio Video Capture and Display

vcu_sdi_xv20

Design showcasing Audio Video Capture and Display through SDI interface along with the capabilities of VCU with PL DDR supporting 4:2:2 10 bit XV20 format encoding from PS DDR and decoding from PL DDR

3

Multi Stream Audio Video Capture and Display

vcu_audio

Design supporting I2S and HDMI Audio with video capture of HDMI-Rx/MIPI-Rx and showcasing capabilities of VCU

4

10G HDMI Video Capture and Display

vcu_10g

Design showcasing Video stream over 10G Ethernet along with the capabilities of VCU

5

PCIe Encode, Decode and Transcode

vcu_pcie

Design to showcase file transfer from HOST(x86) machine over PCIe interface and encode, decode or transcode it on ZCU106 board having VCU connected as PCIe endpoint and write back the encode, decoded or transcoded data to the HOST machine.

6

PL DDR HDR10 HDMI Video Capture and Display

vcu_hdr10_hdmi

VCU based HDMI design to showcase encoding with PS DDR and decoding with PL DDR. It supports the reception and insertion of HDR10 static metadata for HDMI and also DCI4K Feature.

7

Xilinx Low Latency PS DDR NV12 HDMI Audio Video Capture and Display

vcu_llp2_hdmi_nv12

VCU based HDMI audio video design to showcase ultra low latency support using Sync IP, encoding and decoding with PS DDR for NV12 format

8

Xilinx Low Latency PL DDR NV16 HDMI Video Capture and Display

vcu_llp2_hdmi_nv16

VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for NV16 format

9

Xilinx Low Latency PL DDR XV20 HDMI Video Capture and Display

vcu_llp2_hdmi_xv20

VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format

10

Xilinx Low Latency PL DDR XV20 SDI Video Capture and Display

vcu_llp2_sdi_xv20

VCU based SDI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format

11

Quad Sensor MIPI CSI Video Capture and HDMI Display

vcu_quad_sensor

VCU based design supporting Avnet Quad Sensor video capture through MIPI CSI2-Rx and display through HDMI-Tx for NV12 format

VCU TRD User guide has more details about the list of features, software architecture, and hardware architecture of individual designs.

3 Software Tools and System Requirements

3.1 Hardware

Required:

  • ZCU106 evaluation board (rev C/D/E/F/1.0) with power cable

  • Monitor with DisplayPort/HDMI input supporting 4096x2160 or 3840x2160 or 1920x1080 resolution

  • HDR10 supported Monitor with HDMI input supporting 4096x2160 or 3840x2160 or 1920x1080 resolution

  • Display Port cable (DP certified)

  • HDMI cable 2.0 certified

  • Class-10 SD card

  • HDMI Receiver - NVIDIA SHIELD Pro for 4kp60, Panasonic Lumix GH5S