he LogiCORE™ IP Clocking Wizard generates HDL source code to configure a clock circuit to user requirements. The wizard can either automatically select an appropriate clocking primitive and configure buffering, feedback, and timing parameters for a clocking network, or help the user configure the attributes for a manually selected primitive.


Table of Contents

HW IP Features


Known Issues and limitations


Kernel Configuration

. The following steps may be used to enable the driver in the kernel configuration

CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
 
 


Devicetree

  clock-generator@40040000 {
                #clock-cells = <1>;
                reg = <0x40040000 0x1000>;
                compatible = "xlnx,clocking-wizard";
                speed-grade = <1>;
                clock-names = "clk_in1", "s_axi_aclk";
                clocks = <&clkc 15>, <&clkc 15>;
                clock-output-names =  "clk_out1", "clk_out2",
                                     "clk_out3", "clk_out4", "clk_out5",
                                     "clk_out6", "clk_out7";
        };

Test procedure

Mainline Status

Change Log

2023.2

None

2023.1

2022.2


2020.2

None

2022.1

None

2022.2

None

2021.1


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