U-Boot Ethernet Driver

Gigabit Ethernet Controller

Table of Contents

Introduction
U-Boot Config
For ZynqMP:
For Zynq
Device Tree
For ZynqMP
For Zynq
Test Procedure
HW IP features
Features supported in driver
Missing Features, Known Issues and Limitations
Fixed Link Support in ZynqMP

Introduction

The gigabit Ethernet controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC that is compatible with the IEEE Standard for Ethernet (IEEE Std 802.3-2008) and capable of
operating in either half or full-duplex mode in 10/100 mode and full-duplex in 1000 mode. The processing system (PS) is equipped with four gigabit Ethernet controllers. Each
controller can be configured independently. Each controller uses a reduced gigabit media independent interface (RGMII) v2.0 (to save pins).

U-Boot Config

For ZynqMP:

CONFIG_ZYNQ_GEM=y
CONFIG_DM_ETH=y
CONFIG_NET_RANDOM_ETHADDR=y
 

For Zynq

CONFIG_ZYNQ_GEM=y
CONFIG_NET_RANDOM_ETHADDR=y
 

Device Tree


For ZynqMP

&&gem3 {
       status = "okay";
       phy-handle = <&&phy0>;
       phy-mode = "rgmii-id";
       pinctrl-names = "default";
       pinctrl-0 = <&&pinctrl_gem3_default>;
       phy0: phy@21 {
               reg = <21>;
               ti,rx-internal-delay = <0x8>;
               ti,tx-internal-delay = <0xa>;
               ti,fifo-depth = <0x1>;
               ti,rxctrl-strap-worka;
       };
};
 
       pinctrl_gem3_default: gem3-default {
               mux {
                       function = "ethernet3";
                     groups = "ethernet3_0_grp";
               };
 
               conf {
                       groups = "ethernet3_0_grp";
                       slew-rate = <SLEW_RATE_SLOW>;
                       io-standard = <IO_STANDARD_LVCMOS18>;
               };
 
               conf-rx {
                       pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74","MIO75";
                       bias-high-impedance;
                        low-power-disable;
               };
 
               conf-tx {
                       pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68","MIO69";
                       bias-disable;
                       low-power-enable;
               };
 
               mux-mdio {
                       function = "mdio3";
                       groups = "mdio3_0_grp";
               };
 
               conf-mdio {
                       groups = "mdio3_0_grp";
                       slew-rate = <SLEW_RATE_SLOW>;
                       io-standard = <IO_STANDARD_LVCMOS18>;
                       bias-disable;
               };
       };

For Zynq

&&gem0 {
       status = "okay";
       phy-mode = "rgmii-id";
       phy-handle = <&&ethernet_phy>;
       pinctrl-names = "default";
       pinctrl-0 = <&&pinctrl_gem0_default>;
 
       ethernet_phy: ethernet-phy@7 {
               reg = <7>;
               device_type = "ethernet-phy";
       };
};
 
       pinctrl_gem0_default: gem0-default {
               mux {
                       function = "ethernet0";
                       groups = "ethernet0_0_grp";
               };
 
              conf {
                       groups = "ethernet0_0_grp";
                       slew-rate = <0>;
                       io-standard = <4>;
               };
 
               conf-rx {
                      pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
                       bias-high-impedance;
                       low-power-disable;
               };
 
               conf-tx {
                      pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
                       low-power-enable;
                       bias-disable;
               };
 
               mux-mdio {
                       function = "mdio0";
                       groups = "mdio0_0_grp";
               };
 
               conf-mdio {
                       groups = "mdio0_0_grp";
                       slew-rate = <0>;
                       io-standard = <1>;
                       bias-disable;
               };
       };
 

Test Procedure

U-Boot 2018.01 Xilinx ZynqMP ZCU102 rev1.0
 
I2C:   ready
DRAM: 4 GiB
EL Level:       EL2
Chip ID:       zuunknow
** Bad device mmc 0 **
Using default environment
 
In:   serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
Bootmode: JTAG_MODE
Net:   ZYNQ GEM: ff0e0000, phyaddr c, interface rgmii-id
eth0: ethernet@ff0e0000
U-BOOT for xilinx-zcu102-2018_1
 
BOOTP broadcast 1
DHCP client bound to address 10.0.2.15 (3 ms)
Hit any key to stop autoboot: 0
ZynqMP> mii info
PHY 0x07: OUI = 0x5043, Model = 0x21, Rev = 0x00, 1000baseX, FDX
PHY 0x0C: OUI = 0x5043, Model = 0x21, Rev = 0x00, 1000baseX, FDX
ZynqMP>
ZynqMP> mii device
MII devices: 'eth0'
Current device: 'eth0'
ZynqMP>
ZynqMP> setenv <server_ip>
ZynqMP> ping <server_ip>

HW IP features


Features supported in driver

(Functional HW IP and stack related features)

Missing Features, Known Issues and Limitations


Fixed Link Support in ZynqMP

Following are the steps to verify fixed link support in ZynqMP.
Zynq Ultrascale Fixed Link PS Ethernet Demo
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 5cbff57..db256e1 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -124,6 +124,11 @@
ti,fifo-depth = <0x1>;
ti,rxctrl-strap-worka;
};
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
};
 
ZynqMP> setenv ipaddr 192.168.1.1
ZynqMP> ping 192.168.1.10
Using ethernet@ff0e0000 device
host 192.168.1.10 is alive