Table of Contents
The information on this page is specific to Zynq-7000 SoC devices. The Zynq-7000 Programmable Logic (PL) can be programmed either using First Stage Boot-loader (FSBL), U-Boot or through Linux.
This page provides the details about programming the PL from Linux world.
References:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/fpga/fpga-mgr.txt
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.tx
Contiguous Memory Allocator Configuration:
CONFIG_CMA
Select: Memory Management options ---> Contiguous Memory Allocator
CONFIG_DMA_CMA
Library routines--> DMA Contiguous Memory Allocator
devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&&clkc 12>, <&&clkc 15>, <&&clkc 16>, <&&clkc 17>, <&&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&&slcr>; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&&devcfg>; #address-cells = <2>; #size-cells = <2>; }; |
//Device Tree Example: Full Reconfiguration without Bridges // HSI Generated overlay/pl.dtsi file. // Enable the axi-gpio interface /dts-v1/; /plugin/; / { fragment@0 { target = <&&fpga_full>; #address-cells = <1>; #size-cells = <1>; __overlay__ { #address-cells = <1>; #size-cells = <1>; firmware-name = "design_1_wrapper.bit.bin"; }; }; fragment@1 { target = <&&amba>; __overlay__ { axi_gpio_0: gpio@a0000000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x0 0xa0000000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; }; }; }; |
bootgen -image Full_Bitstream.bif -arch zynq -process_bitstream bin |
all: { design_1_wrapper.bit /* Bitstream file name */ } |
// HSI Generated overlay/pl.dtsi file. // Enable the axi-gpio interface /dts-v1/; /plugin/; / { fragment@0 { target = <&&fpga_full>; #address-cells = <1>; #size-cells = <1>; __overlay__ { #address-cells = <1>; #size-cells = <1>; firmware-name = "design_1_wrapper.bit.bin"; }; }; fragment@1 { target = <&&amba>; __overlay__ { axi_gpio_0: gpio@a0000000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x0 0xa0000000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; }; }; }; |
dtc -O dtb -o pl.dtbo -b 0 -@ pl.dtsi |
root@xilinx-zc702-2018_1:/configfs/device-tree/overlays# echo -n "pl.dtbo" > full/path fpga_manager fpga0: writing zc702_wrapper.bit.bin to Xilinx Zynq FPGA Manager XGpio: /amba/gpio@41200000: registered, base is 902 root@xilinx-zc702-2018_1:/configfs/device-tree/overlays# |
Steps for programming the Encrypted Bitstream
1)Set flags for Encrypted Bitstream
2)Load the Bitstream
root@Xilinx:~# mount /dev/mmcblk0p1 /media/ root@Xilinx:~#mkdir -p /lib/firmware root@Xilinx:~# echo 0 > /sys/class/fpga_manager/fpga0/flags root@Xilinx:~# cp /media/system_wrapper.bit.bin /lib/firmware/ root@Xilinx:~# echo system_wrapper.bit.bin > /sys/class/fpga_manager/fpga0/firmware [ 120.266851] fpga_manager fpga0: writing system_wrapper.bit.bin to Xilinx Zynq FPGA Manager root@Xilinx:~# devmem 0xA0000000 0x00000000 |
2021.2
2021.1
2020.2
Summary:
Commits:
2020.1
2019.2
2019.1
2018.3
2018.1