ARM Generic Interrupt Controller
The generic interrupt controller (GIC) is a centralized resource for managing interrupts sent to the
CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interfaceaccepts the next interrupt. In addition, the controller supports security extension for implementing a security-aware system.
The controller is based on the ARM Generic Interrupt Controller Architecture version 1.0 (GIC v1), non-vectored.
The registers are accessed via the CPU private bus for fast read/write response by avoiding temporary blockage or other bottlenecks in interconnect.
The interrupt distributor centralizes all interrupt sources before dispatching the one with the highest priority to the individual CPUs. The GIC ensures that an interrupt targeted to several CPUs can only be taken by one CPU at a time. All interrupt sources are identified by a unique interrupt ID number.
All interrupt sources have their own configurable priority and list of targeted CPUs.
Interrupt Type
Peripheral Interrupt
This is an interrupt asserted by a signal to the GIC. It can be classified in two ways.
1. Private Peripheral Interrupt <or> Shared Peripheral Interrupt
irq_cntlr: interrupt-controller@f8f01000{ compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>; interrupts = <1 9 0xf04>; }; .. .. axi_fifo_mm_s_0: axi_fifo_mm_s@8000c000 compatible = "xlnx,axi-fifo-mm-s-4.1"; interrupt-parent = <&&irq_cntlr>; interrupts = <span style="font-family: Consolas; font-size: 10pt;"><0 96 4>; reg = <0x0 0x8000c000 0x0 0x1000>; xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA"; }; |