Table of Contents

Introduction


This page gives an overview of standalone BSP which is available as part of the Xilinx Vivado and Vitis distribution.

Standalone BSP Sources

The source code for the BSP is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 


Component Name

Path in Vitis

Path in Github

standalone

<Vitis Install Directory>/data/embedded/lib/bsp/standalone

https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/release-2020.1/lib/bsp/standalone


The driver source code is organized into different folders.  The table below shows the standalone BSP source organization. 


Directory
Description

doc

Provides the API and data structure details

data

Driver .tcl and .mld file

examples

Example applications that show how to use the BSP features

src

Driver source files

Overview:

Xilinx provides support for Microblaze, Cortex-A9, Cortex-R5, Cortex-A53 and Cortex-A72 processors.
The standalone BSP performs the processor bring up and provides interface to the user to carry out processor related functionalities naming a few Interrupt enable/disable, device configuration, cache access etc.

To build the BSP, default toolchains are configured with the help of CPU driver. The CPU drivers configure toolchain, archiver and extra compiler flag related settings for a particular bsp. The BSP and drivers are compiled with the same settings. The code for cpu driver can be found at:
cpu_cortexa53 (for Cortex-A53)
cpu_cortexa72 (for Cortex-A72)
cpu_cortexa9 (for Cortex-A9)
cpu_cortexr5 (for Cortex-R5)
cpu (for Microblaze)

The application is built on top of standalone BSP and drivers. The application starts with boot code, doing the processor initialization, soc configuration if required any, toolchain related functionalities if required and reaching to application main. The BSP provide simplified interface to access processor and soc related functionalities.

Features Supported:

ARM Processors (Cortex-A9, Cortex-R5, Cortex-A53, Cortex-A72):

Common Features in ARM BSP:

Cortex-A9 BSP supported features:

Cortex-R5 BSP supported features:


ARMv8 BSP supported features:


Boot Sequence for ARM Processors:

When application software needs to be executed on processor, there are certain configuration needs to be done which are done as part of boot code. When an application is built with Xilinx standalone bsp, following is a sequence illustrating how an application starts and reaches to main function.

MMU/MPU Configuration for ARM Processors

Known issues and Limitations

Example Applications

Refer to the BSP examples directory for various example applications that exercise the different features of the BSP. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. 

Links to Examples

Examples Path:

https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/examples


Test Name

Example Source

Description
Nested interrupt example

xil_nested_interrupts_example.c

Implements example that demonstrates usage of macros available for nested
interrupt handling in xil_exception.h
Cortex-R5 PMU counter example

xpm_counter_r5_example.c

Implements example that demonstrates usage of R5 PMU counters and the
available APIs provided through xpm_counter.c.

Example Application Usage

Nested interrupt example

Implements example that demonstrates usage of macros available for nested interrupt handling in xil_exception.h.  This example can be used on Cortex-A9, Cortex-A53 (64 bit mode), Cortex-A72 (only at EL1 NS) and Cortex-R5
based platforms. 

Expected output


Starting nested timer interrupt example
Nested timer interrupt example passed


Cortex-R5 PMU counter example

Implements example that demonstrates usage of R5 PMU counters and the available APIs provided through xpm_counter.c. This example is applicable only on Cortex-R5 based platforms.

Expected output


Start of R5 PMU Example
Instruction Executed Event Cntr = 100
Data Read Event Cntr = 10
R5 PMU example has PASSED


Changelog

2021.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L291


2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L254

2020.2

2020.1

2019.2

2019.1


2018.3

2018.1

2017.4


2017.3


2017.2

2017.1

2016.4

2016.3


Related Links